Inventor

YEUNG CHUN W

US34 patents

⚠️ This page may combine multiple inventors who share the name “YEUNG CHUN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEUNG CHUN W

IBM

Forming bottom isolation layer for nanosheet technology

Nanosheet FET with wrap-around inner spacer

Sacrificial cap for forming semiconductor contact

Reduced resistance source and drain extensions in vertical field effect transistors

Self-aligned inner-spacer replacement process using implantation

Prevention of extension narrowing in nanosheet field effect transistors

Vertical transport fin field effect transistors having different channel lengths

Airgap spacers

Uniform low-k inner spacer module in gate-all-around (GAA) transistors

Self-limited inner spacer formation for gate-all-around field effect transistors

Prevention of extension narrowing in nanosheet field effect transistors

Sacrificial cap for forming semiconductor contact

Forming bottom isolation layer for nanosheet technology

Reduced resistance source and drain extensions in vertical field effect transistors

Semiconductor device including enhanced low-k spacer

Airgap spacers

Bottom channel isolation in nanosheet transistors

Bottom channel isolation in nanosheet transistors

Silicon residue removal in nanosheet transistors

Gate fill utilizing replacement spacer

Gate fill utilizing replacement spacer

Nanosheet MOSFET with gate fill utilizing replacement spacer

Prevention of extension narrowing in nanosheet field effect transistors

Sacrificial cap for forming semiconductor contact

Self-aligned inner-spacer replacement process using implantation

Reduced resistance source and drain extensions in vertical field effect transistors

Vertical transport fin field effect transistors having different channel lengths

Self-aligned inner-spacer replacement process using implantation

Vertical transport fin field effect transistors having different channel lengths

Airgap spacers

Self-limited inner spacer formation for gate-all-around field effect transistors

Self-limited inner spacer formation for gate-all-around field effect transistors

HEWLETT PACKARD DEVELOPMENT CO

Techniques to reduce radio frequency noise

TESSERA INC

Reduced resistance source and drain extensions in vertical field effect transistors