Inventor

ZHANG JINGYUN

US193 patents

⚠️ This page may combine multiple inventors who share the name “ZHANG JINGYUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHANG JINGYUN

IBM

Multi-threshold voltage gate-all-around field-effect transistor devices with common gates

Stacked field-effect transistors (FETs) with shared and non-shared gates

Nanosheet with selective dipole diffusion into high-k

I/O device for gate-all-around transistors

Nanosheet electrostatic discharge structure

Multiple dielectrics for gate-all-around transistors

Full air-gap spacers for gate-all-around nanosheet field effect transistors

Vertically stacked NFETS and PFETS with gate-all-around structure

Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness

Long channel optimization for gate-all-around transistors

Field-effect transistor unit cells for neural networks with differential weights

Vertically stacked dual channel nanosheet devices

Formation of self-limited inner spacer for gate-all-around nanosheet FET

Method and structure to introduce strain in stack nanosheet field effect transistor

Vertical transport FETs with asymmetric channel profiles using dipole layers

Bottom dielectric isolation structure for nanosheet containing devices

Complementary field-effect transistors

Multi-threshold voltage gate-all-around transistors

Formation of self-limited inner spacer for gate-all-around nanosheet FET

I/O device scheme for gate-all-around transistors

Vertically stacked nFETs and pFETs with gate-all-around structure

Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity

Vertically stacked nFET and pFET with dual work function

Nanosheet single gate (SG) and extra gate (EG) field effect transistor (FET) co-integration

Vertically stacked nFET and pFET with dual work function

Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

Vertically stacked dual channel nanosheet devices

Gate stack optimization for wide and narrow nanosheet transistor devices

Vertically stacked nFET and pFET with dual work function

Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy

Stacked field-effect transistors (FETs) with shared and non-shared gates

Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor

Vertical transport FETs having a gradient threshold voltage

Uniform low-k inner spacer module in gate-all-around (GAA) transistors

Self-limited inner spacer formation for gate-all-around field effect transistors

Semiconductor device and method of forming the semiconductor device

Transistor boundary protection using reversible crosslinking reflow

Formation of wrap-around-contact for gate-all-around nanosheet FET

Complementary FET (CFET) buried sidewall contact with spacer foot

Nanosheet semiconductor devices with n/p boundary structure

Stacked FET multiply and accumulate integrated circuit

Transistor having forked nanosheets with wraparound contacts

ZHANG JINGYUN

Spectrometer miniaturized for working with cellular phones and other portable electronic devices

Spectrometers miniaturized for working with cellular phones and other portable electronic devices

Compact spectrometer

Compact Raman or fluorescence excitation system

CHEMIMAGE CORP

Method and apparatus for microlens array/fiber optics imaging

System and method to perform raman imaging without luminescence

Method and apparatus for reconfigurable field of view in a FAST-based imaging system

COMMISSARIAT ENERGIE ATOMIQUE

Method for making superimposed transistors