Inventor

TITUS MONICA

US16 patents

⚠️ This page may combine multiple inventors who share the name “TITUS MONICA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANDISK TECHNOLOGIES LLC

9 patents

US11621277B2Apr 4, 2023

Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof

SANDISK TECHNOLOGIES LLC5 citations74

US11515250B2Nov 29, 2022

Three dimensional semiconductor device containing composite contact via structures and methods of making the same

SANDISK TECHNOLOGIES LLC1 citations62

US12243776B2Mar 4, 2025

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

SANDISK TECHNOLOGIES LLC0 citations61

US11972954B2Apr 30, 2024

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

SANDISK TECHNOLOGIES LLC0 citations61

US12581656B2Mar 17, 2026

Three-dimensional memory device and method of making thereof using etch stop structures located between tiers

SANDISK TECHNOLOGIES LLC0 citations52

US12010841B2Jun 11, 2024

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

SANDISK TECHNOLOGIES LLC0 citations52

US12261080B2Mar 25, 2025

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

SANDISK TECHNOLOGIES LLC0 citations51

US12245434B2Mar 4, 2025

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

SANDISK TECHNOLOGIES LLC0 citations50

US12250817B2Mar 11, 2025

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

SANDISK TECHNOLOGIES LLC0 citations41

LAM RES CORP

7 patents

US9245761B2Jan 26, 2016

Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

LAM RES CORP15 citations81

US9966270B2May 8, 2018

Gas reaction trajectory control through tunable plasma dissociation for wafer by-product distribution and etch feature profile uniformity

LAM RES CORP2 citations73

US10460951B2Oct 29, 2019

Gas reaction trajectory control through tunable plasma dissociation for wafer by-product distribution and etch feature profile uniformity

LAM RES CORP0 citations52

US9589853B2Mar 7, 2017

Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber

LAM RES CORP0 citations41

TITUS MONICA

SANDISK TECHNOLOGIES LLC

Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof

Three dimensional semiconductor device containing composite contact via structures and methods of making the same

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

Three-dimensional memory device and method of making thereof using etch stop structures located between tiers

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

LAM RES CORP

Internal plasma grid for semiconductor fabrication

Internal plasma grid for semiconductor fabrication

Internal plasma grid applications for semiconductor fabrication

Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

Gas reaction trajectory control through tunable plasma dissociation for wafer by-product distribution and etch feature profile uniformity

Gas reaction trajectory control through tunable plasma dissociation for wafer by-product distribution and etch feature profile uniformity

Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber