Inventor
MISHRA ASIT K
US18 patents
Patents
18 patentsUS10275243B2Apr 30, 2019
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
INTEL CORP23 citations94
US11693691B2Jul 4, 2023
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP4 citations85
US11113053B2Sep 7, 2021
Data element comparison processors, methods, systems, and instructions
INTEL CORP8 citations84
US10489063B2Nov 26, 2019
Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication
INTEL CORP10 citations84
US11416281B2Aug 16, 2022
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP4 citations83
US11093277B2Aug 17, 2021
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP6 citations83
US10275247B2Apr 30, 2019
Apparatuses and methods to accelerate vector multiplication of vector elements having matching indices
INTEL CORP7 citations83
US11698787B2Jul 11, 2023
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
INTEL CORP3 citations73
US10409613B2Sep 10, 2019
Processing devices to perform a key value lookup instruction
INTEL CORP2 citations73
US9996361B2Jun 12, 2018
Byte and nibble sort instructions that produce sorted destination register and destination index mapping
INTEL CORP5 citations73
US12135981B2Nov 5, 2024
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP1 citations72
US12204898B2Jan 21, 2025
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
INTEL CORP0 citations62
US12050912B2Jul 30, 2024
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
INTEL CORP0 citations62
US11048508B2Jun 29, 2021
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
INTEL CORP0 citations62
US10198264B2Feb 5, 2019
Sorting data and merging sorted data in an instruction set architecture
INTEL CORP1 citations59
US10635448B2Apr 28, 2020
Byte and nibble sort instructions that produce sorted destination register and destination index mapping
INTEL CORP0 citations52
US10423411B2Sep 24, 2019
Data element comparison processors, methods, systems, and instructions
INTEL CORP0 citations52
US9405724B2Aug 2, 2016
Reconfigurable apparatus for hierarchical collective networks with bypass mode
INTEL CORP1 citations52