Inventor

MARR DEBORAH T

US30 patents

⚠️ This page may combine multiple inventors who share the name “MARR DEBORAH T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MARR DEBORAH T

INTEL CORP

Method and apparatus for pausing execution in a processor or the like

Method and apparatus for suspending execution of a thread until a specified memory access occurs

Coherency techniques for suspending execution of a thread until a specified memory access occurs

Systems, methods, and apparatuses for heterogeneous computing

Data element comparison processors, methods, systems, and instructions

Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication

Establishing thread priority in a processor or the like

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Apparatuses and methods to accelerate vector multiplication of vector elements having matching indices

Causality-based memory ordering in a multiprocessing environment

Processing devices to perform a key value lookup instruction

Asymmetric performance multicore architecture with same instruction set architecture

Byte and nibble sort instructions that produce sorted destination register and destination index mapping

Dynamic priority external transaction system

Dynamic priority external transaction system

Systems, methods, and apparatuses for heterogeneous computing

Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register

Method and apparatus for pausing execution in a processor or the like

Sorting data and merging sorted data in an instruction set architecture

Asymmetric performance multicore architecture with same instruction set architecture

Byte and nibble sort instructions that produce sorted destination register and destination index mapping

Apparatus and method for processing sparse data

Data element comparison processors, methods, systems, and instructions

Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller

HINTON GLENN J

Controlling non-redundant execution in a redundant multithreading (RMT) processor

Obtaining data for redundant multithreading (RMT) execution

Redundant multithreading processor

GEORGE VARGHESE

Asymmetric performance multicore architecture with same instruction set architecture

MARR DEBORAH T

Establishing thread priority in a processor or the like