Inventor

WILKERSON CHRISTOPHER B

US73 patents

⚠️ This page may combine multiple inventors who share the name “WILKERSON CHRISTOPHER B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WILKERSON CHRISTOPHER B

INTEL CORP

Selective error correction in memory to reduce power consumption

System and method for thread scheduling on reconfigurable processor cores

Runahead allocation protection (RAP)

Spatial footprint prediction

Parallel processing utilizing highly correlated data values

Incorporating trigger loads in branch histories for branch prediction

Least critical used replacement with critical cache

Least recently used replacement method with protection

Decomposition of instructions into branch and sequential code sections

Method and system for performing data movement operations with read snapshot and in place write update

Aggregated write back in a direct mapped two level memory

Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data transfers

Multi-level memory management

System and method to bypass execution of instructions involving unreliable data during speculative execution

Critical loads guided data prefetching

Method and apparatus for implementing a heterogeneous memory subsystem

Method and apparatus for implementing a heterogeneous memory subsystem

Method and system for performing data movement operations with read snapshot and in place write update

Read-write partitioning of cache memory

Parallel processing apparatus, system, and method utilizing correlated data value pairs

Runtime critical load/data ordering

Systems and methods for managing reconfigurable processor cores

Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register

Sequential circuit with error detection

Method and system for performing data movement operations with read snapshot and in place write update

Instruction and logic for run-time evaluation of multiple prefetchers

System and method for cache replacement using conservative set dueling

KEPLER COMPUTING INC

3D stack of accelerator die and multi-core processor die

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

3D stack of split graphics processing logic dies

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

Ferroelectric memory chiplet in a multi-dimensional packaging

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Method and apparatus for managing power in a multi-dimensional packaging

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation

Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing

Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion

Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling

Apparatus and method for endurance of non-volatile memory banks via outlier compensation

Apparatus for improving memory bandwidth through read and restore decoupling

Efficient method for improving memory bandwidth through read and restore decoupling using restore buffer

WILKERSON CHRISTOPHER B

Method and apparatus for using cache memory in a system that supports a low power state

LIU WEI

Methods and apparatuses for efficient load processing using buffers

CHISHTI ZESHAN A

Instruction and logic for run-time evaluation of multiple prefetchers