Inventor

CHISHTI ZESHAN A

US33 patents

⚠️ This page may combine multiple inventors who share the name “CHISHTI ZESHAN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHISHTI ZESHAN A

INTEL CORP

System and method for thread scheduling on reconfigurable processor cores

Techniques to reduce memory cell refreshes for a memory device

Aggregated write back in a direct mapped two level memory

Multi-level memory management

Method and apparatus for implementing a heterogeneous memory subsystem

Method and apparatus for implementing a heterogeneous memory subsystem

Power gating a portion of a cache memory

Power gating a portion of a cache memory

Virtual shared cache mechanism in a processing device

Systems and methods for managing reconfigurable processor cores

Instruction and logic for run-time evaluation of multiple prefetchers

Technologies for memory and I/O efficient operations on homomorphically encrypted data

Processor and method implementing a cacheline demote machine instruction

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

Coarse tag replacement

Multi-level system memory with near memory scrubbing based on predicted far memory idle time

Multi-level memory management

Method and apparatus for pre-fetching data in a system having a multi-level system memory

Constraining prefetch requests to a processor socket

Method and apparatus for multi-level memory early page demotion

Near memory miss prediction to reduce memory access latency

Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory

Sparse superline removal

Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memory

Managing shared cache by multi-core processor

CHISHTI ZESHAN A

Coordinating power mode switching and refresh operations in a memory device

Performing multi-bit error correction on a cache line

Instruction and logic for run-time evaluation of multiple prefetchers

Methods and apparatuses for idle-prioritized memory ranks

ALAMELDEEN ALAA R

Hardware support for thread scheduling on multi-core processors

Dynamically allocatable memory error mitigation

WILKERSON CHRISTOPHER B

Method and apparatus for using cache memory in a system that supports a low power state

KIM CHANGKYU

Virtual row buffers for use with random access memory