Inventor

DEVTA PRASANNA NARENDRA B

US5 patents

⚠️ This page may combine multiple inventors who share the name “DEVTA PRASANNA NARENDRA B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI CORP

2 patents

US8819508B2Aug 26, 2014

Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing

LSI CORP5 citations70

US8352818B2Jan 8, 2013

Method for generating test patterns for small delay defects

LSI CORP4 citations57

DEVTA-PRASANNA NARENDRA B

2 patents

US8412994B2Apr 2, 2013

Design-for-test technique to reduce test volume including a clock gate controller

DEVTA-PRASANNA NARENDRA B6 citations66

US8515695B2Aug 20, 2013

Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC

DEVTA-PRASANNA NARENDRA B1 citations47

GOEL SANDEEP KUMAR

1 patent

US8140923B2Mar 20, 2012

Test circuit and method for testing of infant mortality related defects

GOEL SANDEEP KUMAR3 citations60