Inventor

SHWARTSMAN STANISLAV

IL50 patents

⚠️ This page may combine multiple inventors who share the name “SHWARTSMAN STANISLAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHWARTSMAN STANISLAV

INTEL CORP

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for zeroing a matrix

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile broadcast

Method and apparatus for fine grain memory protection

Microprocessor pipeline circuitry to support cryptographic computing

Method and system to reduce the power consumption of a memory device

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for matrix operations

Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure

Scatter using index array and finite state machine

Gather using index array and finite state machine

Gather using index array and finite state machine

Automatic predication of hard-to-predict convergent branches

Apparatus and method for efficient memory renaming prediction using virtual registers

Device, method and system to predict an address collision by a load and a store

Hardware for split data translation lookaside buffers

Method and apparatus for error correction in a cache

Accelerating memory fault resolution by performing fast re-fetching

Accelerating memory fault resolution by performing fast re-fetching

Criticality based port scheduling

Instruction and logic for store broadcast and power management

Prefetch filter cache for a processor

System, method, and apparatus for enhanced pointer identification and prefetching

System, method, and apparatus for enhanced pointer identification and prefetching

System, method, and apparatus for enhanced pointer identification and prefetching

Systems and methods to predict load data values

Method and apparatus for loop-invariant instruction detection and elimination

Recovery from multiple data errors

Method and apparatus to protect a processor against excessive power usage

Region aware delta prefetcher

Apparatus and method for store pairing with reduced hardware requirements

Thread pause processors, methods, systems, and instructions

Increasing invalid to modified protocol occurrences in a computing system

Sequential data writes to increase invalid to modified protocol occurrences in a computing system

Instruction and logic for register based hardware memory renaming

Instruction and logic for a cache prefetcher and dataless fill buffer

Store forwarding for data caches

SPERBER ZEEV

Gather using index array and finite state machine

Scatter using index array and finite state machine

PARDO ILAN

Snoop filter having centralized translation circuitry and shadow tag array

COHEN EHUD

System and method to reduce power consumption by partially disabling cache memory

RAIKIN SHLOMO

Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register

SHALEV RON

Methods and apparatus for efficient communication between caches in hierarchical caching design

SHWARTSMAN STANISLAV

Method and apparatus for cutting senior store latency using store prefetching