Inventor
Yang sheng wei
US27 patents
⚠️ This page may combine multiple inventors who share the name “Yang sheng wei”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
10 patentsUS11488981B2Nov 1, 2022
Array of vertical transistors and method used in forming an array of vertical transistors
MICRON TECHNOLOGY INC4 citations73
US10854514B2Dec 1, 2020
Microelectronic devices including two contacts
MICRON TECHNOLOGY INC2 citations73
US11444037B2Sep 13, 2022
Semiconductor devices having crack-inhibiting structures
MICRON TECHNOLOGY INC2 citations72
US10811365B2Oct 20, 2020
Semiconductor devices having crack-inhibiting structures
MICRON TECHNOLOGY INC3 citations72
US10784212B2Sep 22, 2020
Semiconductor devices having crack-inhibiting structures
MICRON TECHNOLOGY INC3 citations72
US12336288B2Jun 17, 2025
Array of vertical transistors and method used in forming an array of vertical transistors
MICRON TECHNOLOGY INC0 citations62
US11848282B2Dec 19, 2023
Semiconductor devices having crack-inhibiting structures
MICRON TECHNOLOGY INC0 citations62
US11616028B2Mar 28, 2023
Semiconductor devices having crack-inhibiting structures
MICRON TECHNOLOGY INC0 citations62
US10388564B2Aug 20, 2019
Method for fabricating a memory device having two contacts
MICRON TECHNOLOGY INC1 citations62
US11903183B2Feb 13, 2024
Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices
MICRON TECHNOLOGY INC0 citations59
NANYA TECHNOLOGY CORP
9 patentsUS6946359B2Sep 20, 2005
Method for fabricating trench isolations with high aspect ratio
NANYA TECHNOLOGY CORP31 citations89
US7074700B2Jul 11, 2006
Method for isolation layer for a vertical DRAM
NANYA TECHNOLOGY CORP8 citations71
US9012303B2Apr 21, 2015
Method for fabricating semiconductor device with vertical transistor structure
NANYA TECHNOLOGY CORP0 citations52
US8658538B2Feb 25, 2014
Method of fabricating memory device
NANYA TECHNOLOGY CORP1 citations51
US8647988B2Feb 11, 2014
Memory device and method of fabricating the same
NANYA TECHNOLOGY CORP0 citations51
US6927123B2Aug 9, 2005
Method for forming a self-aligned buried strap in a vertical memory cell
NANYA TECHNOLOGY CORP1 citations51
US6897108B2May 24, 2005
Process for planarizing array top oxide in vertical MOSFET DRAM arrays
NANYA TECHNOLOGY CORP1 citations51
US6958283B2Oct 25, 2005
Method for fabricating trench isolation
NANYA TECHNOLOGY CORP0 citations49
US6962847B2Nov 8, 2005
Method for forming a self-aligned buried strap in a vertical memory cell
NANYA TECHNOLOGY CORP0 citations40