Inventor

LEE JIN-YUAN

TW285 patents

⚠️ This page may combine multiple inventors who share the name “LEE JIN-YUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE JIN-YUAN

MEGIC CORP

Low fabrication cost, high performance, high reliability chip scale package

Low fabrication cost, fine pitch and high reliability solder bump

Method for making high-performance RF integrated circuits

Chip structure and process for forming the same

Post passivation interconnection schemes on top of the IC chips

Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers

Post passivation metal scheme for high-performance integrated circuit devices

Method of making a low fabrication cost, high performance, high reliability chip scale package

Post passivation metal scheme for high-performance integrated circuit devices

Post passivation interconnection schemes on top of the IC chips

Integrated chip package structure using ceramic substrate and method of manufacturing the same

Chip structure and process for forming the same

Chip structure and process for forming the same

Integrated chip package structure using silicon substrate and method of manufacturing the same

Structure of ceramic package with integrated passive devices

High performance system-on-chip using post passivation process and glass substrates

MEGICA CORP

Integrated circuit chips with fine-line metal and over-passivation metal

Integrated circuit chips with fine-line metal and over-passivation metal

Post passivation structure for semiconductor chip or wafer

Integrated chip package structure using organic substrate and method of manufacturing the same

Post passivation method for semiconductor chip or wafer

Bonding structure with pillar and cap

Method of wire bonding over active area of a semiconductor circuit

Structure and manufacturing method of chip scale package

Post passivation interconnection schemes on top of the IC chips

Post passivation interconnection schemes on top of IC chips

Post passivation interconnection schemes on top of the IC chips

Electronic component with die and passive device

Structure of high performance combo chip and processing method

Method for fabricating chip package

Post passivation interconnection schemes on top of the IC chips

TAIWAN SEMICONDUCTOR MFG

Pseudo silicon on insulator MOSFET device

Process of fabrication planarized metallurgy structure for a semiconductor device

Pseudo silicon on insulator MOSFET device

Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer

SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof

Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process

Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures

Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors

Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip

Protective film for fuse window passivation for semiconductor integrated circuit applications

Spin-on-glass partial etchback planarization process

Method of forming a highly transparent silicon rich nitride protective layer for a fuse window

LIN MOU-SHIUNG

System-in packages

Integrated circuit chip using top post-passivation technology and bottom structure technology

System-in packages

Post passivation interconnection schemes on top of IC chip

ICOMETRUE CO LTD

Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells

Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

LEE JIN-YUAN

Low fabrication cost, fine pitch and high reliability solder bump