Inventor

PAUL INDRANI

US55 patents

⚠️ This page may combine multiple inventors who share the name “PAUL INDRANI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAUL INDRANI

ADVANCED MICRO DEVICES INC

Ring networks for intra- and inter-memory I/O including 3D-stacked memories

Balancing computation and communication power in power constrained clusters

Hardware and runtime coordinated load balancing for parallel applications

Thermally-aware throttling in a three-dimensional processor stack

Thermal aware data placement and compute dispatch in a memory system

Technique for extended idle duration for display to improve power consumption

Thermally-aware process scheduling

Core selection based on usage policy and core constraints

Platform power manager for rack level power and thermal constraints

Bandwidth-aware multi-frequency performance estimation mechanism

On-demand IP initialization within power states

Device and method for two-stage transitioning between reduced power states

Method and apparatus for managing power states

Device and method for efficient transitioning to and from reduced power state

Using a hardware-based controller for power state management

Device and method for efficient transitioning to and from reduced power state

Hierarchical state save and restore for device with varying power states

Method and apparatus for temperature and voltage management control

Technique for extended idle duration for display to improve power consumption

Device and method for reducing save-restore latency using address linearization

Method and apparatus for managing power in a thermal couple aware system

Operating voltage adjustment for aging circuits

Operating voltage adjustment for aging circuits

Power management for heterogeneous computing systems

Voltage regulator with programmable telemetry configuration

Platform power manager for rack level power and thermal constraints

Low power state selection based on idle duration history

Low power state selection based on idle duration history

Platform power manager for rack level power and thermal constraints

Distributing power shared between an accelerated processing unit and a discrete graphics processing unit

Memory controller power states

Host controller and bus-attached peripheral device power consumption reduction

Decoupled selective implementation of entry and exit prediction for power gating processor components

Method and apparatus for managing a controller in a power down state

System and method for determining concurrency factors for dispatch size of parallel processor kernels

Power gating based on cache dirtiness

Power efficiency optimization in throughput-based workloads

Hardware accuracy counters for application precision and quality feedback

Controlling electrical power consumption for elements in an electronic device based on a platform electrical power limit

Setting power-state limits based on performance coupling and thermal coupling between entities in a computing device

DELL PRODUCTS LP

Method of processing a circuit board

System and method for dynamically detecting storage drive type

System and method for mapping a logical drive status to a physical drive status for multiple storage drives having different storage technologies within a server

Peripheral component interconnect express root port mirroring

PAUL INDRANI

System and method for multiple backplane time synchronization

System and method for dynamically detecting storage drive type

System and method for multiple backplane time synchronization

Peripheral component interconnect express root port mirroring

LAMBERT TIMOTHY M

System and method for mapping a logical drive status to a physical drive status for multiple storage drives having different storage technologies within a server

ATI TECHNOLOGIES ULC

Method and apparatus for providing non-compute unit power control in integrated circuits