Inventor

CAMP CHARLES J

US105 patents

⚠️ This page may combine multiple inventors who share the name “CAMP CHARLES J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAMP CHARLES J

IBM

Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory

Metadata hardening and parity accumulation for log-structured arrays

Mitigating read errors following programming in a multi-level non-volatile memory

Recovery of multi-page failures in non-volatile memory system

Dynamically optimizing flash data retention or endurance based on data write frequency

Flash memory codeword architectures

Regrouping data during relocation to facilitate write amplification reduction

Endurance enhancement scheme using memory re-evaluation

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

Reducing read disturb effect on partially programmed blocks of non-volatile memory

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Non-volatile memory controller cache architecture with support for separation of data streams

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

Collaborative health management in a storage system

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Promoting consistent response times in a data storage system having multiple data retrieval mechanisms

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

Extending useful life of a non-volatile memory by health grading

Secure memory system with fast wipe feature

Efficient management of page retirement in non-volatile memory utilizing page retirement classes

Physical address management in solid state memory

Reducing read-after-write errors in a non-volatile memory system using an old data copy

Page retirement in a NAND flash memory system

Efficient reduction of read disturb errors

Memory system with variable length page stripes including data protection information

Reduction of read disturb errors

Device for selecting a level for at least one read voltage

Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems

Page retirement in a NAND flash memory system

Techniques for dynamically adjusting over-provisioning space of a flash controller based on workload characteristics

Non-volatile memory controller cache architecture with support for separation of data streams

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

Storage array management employing a merged background management process

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

FROST HOLLOWAY H

Method and apparatus for addressing actual or predicted failures in a FLASH-based storage system

FLASH-based memory system with variable length page stripes including data protection information

Secure Flash-based memory system with fast wipe feature

FLASH-based memory system with static or variable length page stripes including data protection information and auxiliary protection stripes

Secure Flash-based memory system with fast wipe feature

Efficient reduction of read disturb errors in NAND flash memory

Flash-based memory system with variable length page stripes including data protection information

Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system

Efficient reduction of read disturb errors in NAND FLASH memory

Method and apparatus for addressing actual or predicted failures in a flash-based storage system

TEXAS MEMORY SYSTEMS INC

Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system

Efficient reduction of read disturb errors in NAND FLASH memory

Flash-based memory system with static or variable length page stripes including data protection information and auxiliary protection stripes

Method and apparatus for clock calibration in a clocked digital device

CAMP CHARLES J

Reduction of read disturb errors in NAND FLASH memory

Reduction of read disturb errors in NAND FLASH memory