Inventor

PLETKA ROMAN

CH33 patents

⚠️ This page may combine multiple inventors who share the name “PLETKA ROMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PLETKA ROMAN

IBM

Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory

Mitigating read errors following programming in a multi-level non-volatile memory

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

Techniques for retention and read-disturb aware health binning

Reducing read disturb effect on partially programmed blocks of non-volatile memory

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Non-volatile memory controller cache architecture with support for separation of data streams

Non-volatile memory data storage with low read amplification

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

Scheduling requests in a solid state memory device

Non-volatile memory controller cache architecture with support for separation of data streams

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

Non-volatile memory system having an increased effective number of supported heat levels

Processing unit reclaiming requests in a solid state memory device

Selectively enabling write caching in a storage system based on performance metrics

Managing cache memories

Scheduling requests in a solid state memory device

Non-volatile memory controller cache architecture with support for separation of data streams

Endurance enhancement scheme using memory re-evaluation

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

Reducing read access latency by straddling pages across non-volatile memory channels

Processing unit reclaiming requests in a solid state memory device

Managing metadata for caching devices during shutdown and restart procedures

ELEFTHERIOU EVANGELOS S

Optimizing locations of data accessed by client applications interacting with a storage system

Optimizing locations of data accessed by client applications interacting with a storage system

CIDECIYAN ROY D

Wear-level of cells/pages/sub-pages/blocks of a memory

Method, device and computer program product for decoding a codeword

ILIADIS ILIAS

Intra-block memory wear leveling

BUX WERNER

Logical to physical address mapping in storage systems comprising solid state memory devices

KOLTSIDAS IOANNIS

Write cache structure in a storage system

HAAS ROBERT

Method and controller for identifying a unit in a solid state memory device for writing data to