Inventor
WALLS ANDREW D
US98 patents
⚠️ This page may combine multiple inventors who share the name “WALLS ANDREW D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
43 patentsUS10437670B1Oct 8, 2019
Metadata hardening and parity accumulation for log-structured arrays
IBM66 citations96
US9496043B1Nov 15, 2016
Dynamically optimizing flash data retention or endurance based on data write frequency
IBM41 citations94
US5603044AFeb 11, 1997
Interconnection network for a multi-nodal data processing system which exhibits incremental scalability
IBM148 citations94
US7409600B2Aug 5, 2008
Self-healing cache system
IBM27 citations92
US7404017B2Jul 22, 2008
Method for managing data flow through a processing system
IBM37 citations91
US7003409B2Feb 21, 2006
Predictive failure analysis and failure isolation using current sensing
IBM23 citations91
US7171576B2Jan 30, 2007
Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency
IBM29 citations90
US5533194AJul 2, 1996
Hardware-assisted high speed memory test apparatus and method
IBM42 citations87
US11264103B2Mar 1, 2022
Hybrid read voltage calibration in non-volatile random access memory
IBM12 citations86
US11023150B2Jun 1, 2021
Block mode toggling using hybrid controllers
IBM11 citations86
US9779021B2Oct 3, 2017
Non-volatile memory controller cache architecture with support for separation of data streams
IBM8 citations84
US9619381B2Apr 11, 2017
Collaborative health management in a storage system
IBM14 citations84
US9569118B2Feb 14, 2017
Promoting consistent response times in a data storage system having multiple data retrieval mechanisms
IBM8 citations84
US9558107B2Jan 31, 2017
Extending useful life of a non-volatile memory by health grading
IBM17 citations84
US9367250B2Jun 14, 2016
Enabling throttling on average write throughput for solid state storage devices
IBM7 citations84
US9348518B2May 24, 2016
Buffered automated flash controller connected directly to processor memory bus
IBM10 citations84
US9274882B2Mar 1, 2016
Page retirement in a NAND flash memory system
IBM8 citations84
US8868875B2Oct 21, 2014
Enabling throttling on average write throughput for solid state storage devices
IBM4 citations84
US8819333B2Aug 26, 2014
Using the short stroked portion of hard disk drives for a mirrored copy of solid state drives
IBM5 citations84
US7954021B2May 31, 2011
Solid state drive with flash sparing
IBM9 citations84
US9690801B1Jun 27, 2017
Techniques for improving deduplication efficiency in a storage system with multiple storage nodes
IBM9 citations83
US9280419B2Mar 8, 2016
Dynamic adjustment of data protection schemes in flash storage systems based on temperature, power off duration and flash age
IBM10 citations83
US7231501B2Jun 12, 2007
Method for avoiding aliased tokens during abnormal communications
IBM11 citations83
US7562265B2Jul 14, 2009
Method, apparatus and program storage device for providing self-quiesced logic to handle an error recovery instruction
IBM8 citations81
US4785452ANov 15, 1988
Error detection using variable field parity checking
IBM21 citations76
US12222800B2Feb 11, 2025
Write and retire pages in QLC NAND blocks
IBM2 citations75
US12093171B2Sep 17, 2024
Proactive data placement in high density storage by a hybrid non-volatile storage controller
IBM2 citations73
US11182089B2Nov 23, 2021
Adapting memory block pool sizes using hybrid controllers
IBM2 citations73
US10977181B2Apr 13, 2021
Data placement in write cache architecture supporting read heat data separation
IBM2 citations73
US10733069B2Aug 4, 2020
Page retirement in a NAND flash memory system
IBM2 citations73
US10459808B2Oct 29, 2019
Data storage system employing a hot spare to store and service accesses to data having lower associated wear
IBM3 citations73
US10387317B2Aug 20, 2019
Non-volatile memory controller cache architecture with support for separation of data streams
IBM2 citations73
US9952795B2Apr 24, 2018
Page retirement in a NAND flash memory system
IBM3 citations73
US9785575B2Oct 10, 2017
Optimizing thin provisioning in a data storage system through selective use of multiple grain sizes
IBM2 citations73
US9727244B2Aug 8, 2017
Expanding effective storage capacity of a data storage system while providing support for address mapping recovery
IBM4 citations73
US9653185B2May 16, 2017
Reducing error correction latency in a data storage system having lossy storage media
IBM4 citations73
US9632702B2Apr 25, 2017
Efficient initialization of a thinly provisioned storage array
IBM2 citations73
US9619158B2Apr 11, 2017
Two-level hierarchical log structured array architecture with minimized write amplification
IBM6 citations73
US9606734B2Mar 28, 2017
Two-level hierarchical log structured array architecture using coordinated garbage collection for flash arrays
IBM6 citations73
US9542284B2Jan 10, 2017
Buffered automated flash controller connected directly to processor memory bus
IBM2 citations73
US9170943B2Oct 27, 2015
Selectively enabling write caching in a storage system based on performance metrics
IBM6 citations73
US7490205B2Feb 10, 2009
Method for providing a triad copy of storage data
IBM5 citations73
US10235396B2Mar 19, 2019
Workload optimized data deduplication using ghost fingerprints
IBM2 citations72
FISKE RAHUL M
2 patentsBENHASE MICHAEL T
2 patentsCAGNO BRIAN J
1 patentBENHASE MICHAEL THOMAS
1 patentTRESSLER GARY A
1 patentShowing the top 50 of 98 patents by PatentIndex Score.