P

Inventor

BURTON RICHARD

US35 patents
⚠️ This page may combine multiple inventors who share the name “BURTON RICHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ATOMERA INC

32 patents
US10868120B1Dec 15, 2020

Method for making a varactor with hyper-abrupt junction region including a superlattice

ATOMERA INC31 citations94
US10854717B2Dec 1, 2020

Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance

ATOMERA INC32 citations94
US10847618B2Nov 24, 2020

Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance

ATOMERA INC33 citations94
US10840336B2Nov 17, 2020

Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods

ATOMERA INC31 citations94
US10840388B1Nov 17, 2020

Varactor with hyper-abrupt junction region including a superlattice

ATOMERA INC33 citations94
US10840335B2Nov 17, 2020

Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance

ATOMERA INC31 citations94
US10840337B2Nov 17, 2020

Method for making a FINFET having reduced contact resistance

ATOMERA INC31 citations94
US10825901B1Nov 3, 2020

Semiconductor devices including hyper-abrupt junction region including a superlattice

ATOMERA INC32 citations94
US10825902B1Nov 3, 2020

Varactor with hyper-abrupt junction region including spaced-apart superlattices

ATOMERA INC30 citations94
US10818755B2Oct 27, 2020

Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance

ATOMERA INC33 citations94
US10593761B1Mar 17, 2020

Method for making a semiconductor device having reduced contact resistance

ATOMERA INC51 citations94
US10580866B1Mar 3, 2020

Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance

ATOMERA INC49 citations94
US10580867B1Mar 3, 2020

FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance

ATOMERA INC49 citations94
US11387325B2Jul 12, 2022

Vertical semiconductor device with enhanced contact structure and associated methods

ATOMERA INC12 citations93
US11329154B2May 10, 2022

Semiconductor device including a superlattice and an asymmetric channel and related methods

ATOMERA INC14 citations93
US11094818B2Aug 17, 2021

Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods

ATOMERA INC18 citations93
US11075078B1Jul 27, 2021

Method for making a semiconductor device including a superlattice within a recessed etch

ATOMERA INC21 citations93
US10879356B2Dec 29, 2020

Method for making a semiconductor device including enhanced contact structures having a superlattice

ATOMERA INC21 citations93
US10777451B2Sep 15, 2020

Semiconductor device including enhanced contact structures having a superlattice

ATOMERA INC30 citations93
US11935940B2Mar 19, 2024

Methods for making bipolar junction transistors including emitter-base and base-collector superlattices

ATOMERA INC6 citations86
US11923431B2Mar 5, 2024

Bipolar junction transistors including emitter-base and base-collector superlattices

ATOMERA INC6 citations86
US11437487B2Sep 6, 2022

Bipolar junction transistors including emitter-base and base-collector superlattices

ATOMERA INC8 citations86
US11437486B2Sep 6, 2022

Methods for making bipolar junction transistors including emitter-base and base-collector superlattices

ATOMERA INC8 citations86
US11183565B2Nov 23, 2021

Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods

ATOMERA INC15 citations86
US10937868B2Mar 2, 2021

Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices

ATOMERA INC19 citations86
US10937888B2Mar 2, 2021

Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices

ATOMERA INC19 citations86
US10879357B1Dec 29, 2020

Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice

ATOMERA INC19 citations86
US11869968B2Jan 9, 2024

Semiconductor device including a superlattice and an asymmetric channel and related methods

ATOMERA INC8 citations85
US11664427B2May 30, 2023

Vertical semiconductor device with enhanced contact structure and associated methods

ATOMERA INC7 citations85
US12439618B2Oct 7, 2025

Bipolar junction transistors including emitter-base and base-collector superlattices

ATOMERA INC0 citations62
US12199180B2Jan 14, 2025

Semiconductor device including a superlattice and an asymmetric channel and related methods

ATOMERA INC0 citations62
US12382689B2Aug 5, 2025

Method for making DMOS devices including a superlattice and field plate for drift region diffusion

ATOMERA INC0 citations50

BURTON ALUMINUM CLASSICS INC

1 patent

BURTON RICHARD

1 patent

GILLETTE CO

1 patent