Inventor
RENAULD VIVIEN
FR4 patents
Patents
4 patentsUS7601606B2Oct 13, 2009
Method for reducing the trap density in a semiconductor wafer
SOITEC SILICON ON INSULATOR2 citations56
US7544058B2Jun 9, 2009
Method for high-temperature annealing a multilayer wafer
SOITEC SILICON ON INSULATOR0 citations49
US7585793B2Sep 8, 2009
Method for applying a high temperature heat treatment to a semiconductor wafer
SOITEC SILICON ON INSULATOR0 citations39
US9583341B2Feb 28, 2017
Layer transferring process
SOITEC SILICON ON INSULATOR0 citations27