Inventor
MASTRONARDE JOSH B
US36 patents
Patents
36 patentsUS7051172B2May 23, 2006
Memory arbiter with intelligent page gathering logic
INTEL CORP30 citations92
US6792516B2Sep 14, 2004
Memory arbiter with intelligent page gathering logic
INTEL CORP26 citations92
US11094033B2Aug 17, 2021
Reduce power by frame skipping
INTEL CORP6 citations84
US10891773B2Jan 12, 2021
Apparatus and method for efficient graphics virtualization
INTEL CORP8 citations84
US10417731B2Sep 17, 2019
Compute optimization mechanism for deep neural networks
INTEL CORP8 citations84
US7035984B2Apr 25, 2006
Memory arbiter with grace and ceiling periods and intelligent page gathering logic
INTEL CORP12 citations84
US9250910B2Feb 2, 2016
Current change mitigation policy for limiting voltage droop in graphics logic
INTEL CORP10 citations79
US12198221B2Jan 14, 2025
Compute optimization mechanism for deep neural networks
INTEL CORP1 citations75
US11494868B2Nov 8, 2022
Contextual configuration adjuster for graphics
INTEL CORP1 citations73
US11222392B2Jan 11, 2022
Compute optimization mechanism for deep neural networks
INTEL CORP1 citations73
US10929947B2Feb 23, 2021
Contextual configuration adjuster for graphics
INTEL CORP2 citations73
US10902547B2Jan 26, 2021
Compute optimization mechanism for deep neural networks
INTEL CORP2 citations73
US10565671B2Feb 18, 2020
Reduce power by frame skipping
INTEL CORP2 citations73
US10521880B2Dec 31, 2019
Adaptive compute size per workload
INTEL CORP1 citations73
US10460415B2Oct 29, 2019
Contextual configuration adjuster for graphics
INTEL CORP3 citations73
US10430310B2Oct 1, 2019
Dynamic voltage-frequency curve management
INTEL CORP5 citations73
US6593931B1Jul 15, 2003
Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles
INTEL CORP7 citations71
US11922535B2Mar 5, 2024
Compute optimization mechanism for deep neural networks
INTEL CORP0 citations63
US11593910B2Feb 28, 2023
Compute optimization mechanism for deep neural networks
INTEL CORP0 citations63
US11562461B2Jan 24, 2023
Compute optimization mechanism for deep neural networks
INTEL CORP0 citations63
US11416962B2Aug 16, 2022
Adaptive compute size per workload
INTEL CORP0 citations63
US11348198B2May 31, 2022
Compute optimization mechanism for deep neural networks
INTEL CORP0 citations63
US11334962B2May 17, 2022
Compute optimization mechanism for deep neural networks
INTEL CORP0 citations63
US11048605B2Jun 29, 2021
Dynamic voltage-frequency curve mangement
INTEL CORP0 citations63
US10963986B2Mar 30, 2021
Adaptive compute size per workload
INTEL CORP0 citations63
US12205192B2Jan 21, 2025
Reduce power by frame skipping
INTEL CORP0 citations62
US11989076B2May 21, 2024
Dynamically power on/off processing clusters during execution
INTEL CORP0 citations62
US11762696B2Sep 19, 2023
Hybrid low power homogenous grapics processing units
INTEL CORP0 citations62
US11475623B2Oct 18, 2022
Apparatus and method for efficient graphics virtualization
INTEL CORP0 citations62
US11169850B2Nov 9, 2021
Hybrid low power homogenous grapics processing units
INTEL CORP0 citations62
US11106274B2Aug 31, 2021
Adjusting graphics rendering based on facial expression
INTEL CORP1 citations62
US10528118B2Jan 7, 2020
Dynamically power on/off register files during execution
INTEL CORP1 citations62
US10521271B2Dec 31, 2019
Hybrid low power homogenous grapics processing units
INTEL CORP0 citations52
US10417734B2Sep 17, 2019
Compute optimization mechanism for deep neural networks
INTEL CORP0 citations52
US6510472B1Jan 21, 2003
Dual input lane reordering data buffer
INTEL CORP0 citations52
US10503520B2Dec 10, 2019
Automatic waking of power domains for graphics configuration requests
INTEL CORP0 citations34