Inventor

CHOI JUNGWOOK

KR29 patents

⚠️ This page may combine multiple inventors who share the name “CHOI JUNGWOOK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI JUNGWOOK

IBM

Loop management in multi-processor dataflow architecture

Neural network circuitry having floating point format with asymmetric range

Mixed precision capable hardware for tuning a machine learning model

System-aware selective quantization for performance optimized distributed deep learning

Robust gradient weight compression schemes for deep learning applications

Hybrid floating point representation for deep learning acceleration

Very low precision floating point representation for deep learning acceleration

Matrix multiplication on a systolic array

Matrix multiplication on a systolic array

Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction

Hybrid floating point representation for deep learning acceleration

Statistics-aware weight quantization

Dynamically resizing minibatch in neural network execution

Reduced precision based programmable and SIMD dataflow architecture

Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components

Facilitating neural network efficiency

Machine learning hardware having reduced precision parameter components for efficient parameter update

Method to map convolutional layers of deep neural network on a plurality of processing elements with SIMD execution units, private memories, and connected as a 2D systolic processor array

Low precision deep neural network enabled by compensation instructions

Formation failure resilient neuromorphic device

Deep neural network performance analysis on shared memory accelerator systems

Compression of fully connected / recurrent layers of deep network(s) through enforcing spatial locality to weight matrices and effecting frequency compression

Processor and memory transparent convolutional lowering and auto zero padding for deep neural network implementations

Matrix multiplication on a systolic array

Matrix multiplication on a systolic array

Deep learning accelerator architecture with chunking GEMM

SAMSUNG ELECTRONICS CO LTD

Method for transmitting data and electronic device using the same

INDUSTRY-ACADEMIC COOPERATION FOUNDATION YONSEI UNIV

Method for implanted-ion assisted growth of metal oxide nanowires and patterned device fabricated using the method

KIM JONGBAEG

Micro structure, micro actuators, method of fabricating micro structure and micro actuators