Inventor

CHANG JONATHAN TSUNG-YUNG

TW115 patents

⚠️ This page may combine multiple inventors who share the name “CHANG JONATHAN TSUNG-YUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG JONATHAN TSUNG-YUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Pre-colored methodology of multiple patterning

Memory macro and method of operating the same

Negative bitline boost scheme for SRAM write-assist

Negative bitline boost scheme for SRAM write-assist

Method of forming semiconductor device including distributed write driving arrangement

Semiconductor device including distributed write driving arrangement and method of operating same

Memory computation circuit and method

Low voltage memory device

Semiconductor device including distributed write driving arrangement and method of operating same

Memory macro and method of operating the same

Memory device with strap cells

Configurable memory storage system

Memory macro and method of operating the same

Memory device with strap cells

Memory macro and method of operating the same

Memory read stability enhancement with short segmented bit line architecture

Memory device with strap cells

Semiconductor device structure and method for forming the same

Memory devices with strap cells

Pre-colored methodology of multiple patterning

High density memory structure

Method and apparatus for read assist to compensate for weak bit

Method of differentiated thermal throttling of memory and system therefor

Memory macro including through-silicon via

Semiconductor device including distributed write driving arrangement

Memory macro and method of operating the same

Memory cell including programmable resistors with transistor components

Memory macro including through-silicon via

Low voltage memory device

Configurable memory storage system

Memory macro and method of operating the same

Configurable memory storage system

Low voltage bit-cell

Memory circuit having resistive device coupled with supply voltage line

Memory read stability enhancement with short segmented bit line architecture

Systems and methods to test a memory device

Method of writing to memory circuit using resistive device

Power switch control for dual power supply

Memory read stability enhancement with short segmented bit line architecture

Memory circuit having resistive device coupled with supply voltage line

Memory with write assist circuit

Memory with bit line control

CHANG JONATHAN TSUNG-YUNG

Method and apparatus for word line suppression

Memory cell having flexible read/write assist and method of using

Method and apparatus for read assist to compensate for weak bit

TAIWAN SEMICONDUCTOR MFG

Write assist circuit, memory device and method

Voltage divider control circuit

CHENG CHITING

SRAM read and write assist apparatus

CHEN YEN-HUEI

Pre-colored methodology of multiple patterning

LIN CHIH-YU

Memory circuit and method of writing datum to memory circuit