Inventor

DEVILLIERS ANTON J

US135 patents

⚠️ This page may combine multiple inventors who share the name “DEVILLIERS ANTON J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DEVILLIERS ANTON J

TOKYO ELECTRON LTD

Buried power rails

Semiconductor apparatus having stacked gates and method of manufacture thereof

Three-dimensional semiconductor device and method of fabrication

Extension region for a semiconductor device

Self-alignment of metal and via using selective deposition

Method of pattern alignment for field stitching

Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication

Power distribution network for 3D logic and memory

Extension region for a semiconductor device

Location-specific tuning of stress to control bow to control overlay in semiconductor processing

Location-specific tuning of stress to control bow to control overlay in semiconductor processing

Location-specific tuning of stress to control bow to control overlay in semiconductor processing

Method for correcting wafer bow from overlay

Methods of forming etch masks for sub-resolution substrate patterning

Direct current superposition freeze

Critical dimension control in photo-sensitized chemically-amplified resist

Method for multiplying pattern density by crossing multiple patterned layers

Location-specific tuning of stress to control bow to control overlay in semiconductor processing

Location-specific tuning of stress to control bow to control overlay in semiconductor processing

3D complementary metal oxide semiconductor (CMOS) device and method of forming the same

Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device

Method to form narrow slot contacts

Method for producing overlay results with absolute reference for semiconductor manufacturing

Reverse contact and silicide process for three-dimensional logic devices

Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

Architecture for monolithic 3D integration of semiconductor devices

High performance circuit applications using stacked 3D metal lines

System and method for fluid dispense and coverage control

Critical dimension control by use of photo-sensitized chemicals or photo-sensitized chemically amplified resist

Critical dimension control by use of a photo agent

System and method for planarizing a substrate

System and method for temperature control in plasma processing system

Methods of forming etch masks for sub-resolution substrate patterning

Critical dimension control by use of a photo agent

Methods of forming a mask for substrate patterning

Method and system for a spiral mixer

Methods of forming etch masks for sub-resolution substrate patterning

Method of patterning without dummy gates

Methods for treating a substrate by optical projection of a correction pattern based on a detected spatial heat signature of the substrate

Substrate tuning system and method using optical projection

Patterning a substrate using grafting polymer material

Method for patterning a substrate for planarization

Method for patterning contact openings on a substrate

Method and system for forming memory fin patterns

System and method for shifting critical dimensions of patterned films

Substrate backside texturing

MICRON TECHNOLOGY INC

Semiconductor device structures

Methods of forming features in semiconductor device structures

SIPANI VISHAL

Methods of forming a pattern on a substrate

LIGHT SCOTT L

Methods of forming a pattern on a substrate