Inventor

CHEN KANG

CN168 patents

⚠️ This page may combine multiple inventors who share the name “CHEN KANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN KANG

STATS CHIPPAC LTD

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP

Semiconductor package with semiconductor core structure and method of forming same

Semiconductor device and method of forming high-frequency circuit structure and method thereof

Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor device and method of forming a PoP device with embedded vertical interconnect units

Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package

Semiconductor device and method of forming microelectromechanical systems (MEMS) package

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

Semiconductor device including integrated passive device formed over semiconductor die with conductive bridge and fan-out redistribution layer

Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die

Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die

Semiconductor device and method of forming integrated passive device module

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB

Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP

Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units

Semiconductor device and method of forming build-up interconnect structures over a temporary substrate

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages

Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package

Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)

LIN YAOJIAN

Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor package with semiconductor core structure and method of forming the same

Semiconductor device and method of forming interconnect substrate for FO-WLCSP

Semiconductor device and method of forming an embedded SOP fan-out package

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor package with semiconductor core structure and method of forming same

Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation

Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP

Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief

Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer

STATS CHIPPAC PTE LTD

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

Semiconductor device and method of forming build-up interconnect structures over a temporary substrate

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming an embedded SoP fan-out package

TYPEFACE INC

Interactive prompting system for multimodal personalized content generation

Interactive canvas tool for multimodal personalized content generation

Enhancement of machine-generated product image

QIU PENG

Bounce attack prevention based on e-mail message tracking

CHEN KANG

Outdoor electrical box