Inventor

NARAYANAN PRITISH

US28 patents

⚠️ This page may combine multiple inventors who share the name “NARAYANAN PRITISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARAYANAN PRITISH

IBM

Controlling aggregate signal amplitude from device arrays by segmentation and time-gating

Analog-to-digital conversion with reconfigurable function mapping for neural networks activation function acceleration

High memory bandwidth neuromorphic computing system

Two-dimensional mesh for compute-in-memory accelerator architecture

Split pulse width modulation to reduce crossbar array integration time

System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Selective application of multiple pulse durations to crossbar arrays

Competitive machine learning accuracy on neuromorphic arrays with non-ideal non-volatile memory devices

System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Mitigation of conductance drift in neural network resistive processing units

Configuring computing nodes in a three-dimensional mesh topology

Distributing device array currents across segment mirrors

Configuring computing nodes in a three-dimensional mesh topology

Apparatus for deep learning operations on resistive crossbar array

Implicit vector concatenation within 2D mesh routing

Compression of fully connected / recurrent layers of deep network(s) through enforcing spatial locality to weight matrices and effecting frequency compression

System and method for transfer of analog synaptic weight information onto neuromorphic arrays with non-ideal non-volatile memory device

Temporal memory adapted for single-shot learning and disambiguation of multiple predictions

Controlling aggregate signal amplitude from device arrays by segmentation and time-gating

Row-by-row convolutional neural network mapping for analog artificial intelligence network training

Magnetic domain wall-based non-volatile, linear and bi-directional synaptic weight element

Hardware implementation of activation functions

Programming devices and weights in hardware

Closed loop programming of phase-change memory

Analog memory-based complex multiply-accumulate (MACC) compute engine

INT BUSINESS MACHINES CORPORATION

Stochastic bitstream generation with in-situ function mapping