Inventor

WU HENG

US194 patents

⚠️ This page may combine multiple inventors who share the name “WU HENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU HENG

IBM

Vertical field-effect transistor with uniform bottom spacer

Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices

Buried power and ground in stacked vertical transport field effect transistors

Leakage control for gate-all-around field-effect transistor devices

Inverse T-shaped contact structures having air gap spacers

Formation of stacked nanosheet semiconductor devices

Nanosheet transistor

Tunnel transistor

Wrapped source/drain contacts with enhanced area

Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

Transistor with asymmetric spacers

Inverse T-shaped contact structures having air gap spacers

Stacked spin-orbit-torque magnetoresistive random-access memory

Stacked nanosheet CFET with gate all around structure

Formation of air gap spacers for reducing parasitic capacitance

Formation of stacked nanosheet semiconductor devices

Nanosheet transistors with inner airgaps

Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

Vertical field-effect transistors including uniform gate lengths

Transistor with asymmetric source/drain overlap

Self-limited inner spacer formation for gate-all-around field effect transistors

Magnetic tunnel junction device with minimum stray field

Nanosheet transistors with inner airgaps

Integrating embedded memory on CMOS logic using thin film transistors

Phase change memory using multiple stacks of PCM materials

Contact resistance reduction in nanosheet device structure

Stacked gate structures

Nanosheet transistor having wrap-around bottom isolation

VTFET with cell height constraints

Formation of air gap spacers for reducing parasitic capacitance

Stacked vertical field effect transistor with self-aligned junctions

Self-aligned bottom spacer EPI last flow for VTFET

Stacked upper fin and lower fin transistor with separate gate

Contact formation for stacked vertical transport field-effect transistors

Silicide formation for source/drain contact in a vertical transport field-effect transistor

Spin-orbit-torque magneto-resistive random access memory with stepped bottom electrode

Reducing gate resistance in stacked vertical transport field effect transistors

Formation of stacked vertical transport field effect transistors

Forming an MRAM device over a transistor

Formation of a partial air-gap spacer

Stacked vertical transistor memory cell with epi connections

Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization

TESSERA INC

Nanosheet transistor

Nanosheet transistor

GEN ELECTRIC

System and method for fault protection of a motor

WU HENG

Portable battery

SHENZHEN MAGNET TECH CO LTD

Hearing aid

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Nanosheet transistor