Inventor

PENDSE RAJENDRA D

US143 patents

⚠️ This page may combine multiple inventors who share the name “PENDSE RAJENDRA D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENDSE RAJENDRA D

STATS CHIPPAC LTD

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Bump-on-lead flip chip interconnection

Method of forming a bump-on-lead flip chip interconnection having higher escape routing density

Bump-on-lead flip chip interconnection

Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration

Semiconductor device and method of forming electrical interconnect with stress relief void

Package-on-package system

Semiconductor device and method of forming pad layout for flipchip semiconductor die

Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits

Semiconductor device and method of forming wire bondable fan-out EWLB package

Semiconductor package with embedded die

Semiconductor device and method of forming bump-on-lead interconnection

Flip chip interconnection having narrow interconnection sites on the substrate

Semiconductor device and method of forming bump-on-lead interconnection

PENDSE RAJENDRA D

Flip chip interconnection having narrow interconnection sites on the substrate

Semiconductor package with embedded die

Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate

Bump-on-lead flip chip interconnection

Integrated circuit package system for package stacking and method of manufacture therefor

Semiconductor device and method of forming composite bump-on-lead interconnection

Solder joint flip chip interconnection

Solder joint flip chip interconnection having relief structure

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate

Solder joint flip chip interconnection

Flip chip interconnection structure

Semiconductor device and method of forming bump-on-lead interconnection

HEWLETT PACKARD CO

Cost effective structure and method for interconnecting a flip chip with a substrate

High temperature flip chip joining flux that obviates the cleaning process

High pin count package for semiconductor device

Method for forming a controlled impedance flex circuit

Apparatus and method for precise alignment of a ceramic module to a test apparatus

Radially staggered bond pad arrangements for integrated circuit pad circuitry

Tab frame with area array edge contacts

Integrated circuit demountable TAB apparatus

CHIPPAC INC

Flip chip interconnection structure

Method of forming flip chip interconnection structure

Bump-on-lead flip chip interconnection

Flip chip interconnection pad layout

Wire bond interconnection

Flip chip-in-leadframe package and process

(unassigned)

Direct chip connection using demountable flip chip package

Method for making high pin count package for semiconductor device

System and method for forming a controlled impedance flex circuit

STATS CHIPPAC INC

Multi-layer semiconductor package

Multi-layer semiconductor package with vertical connectors and method of manufacture thereof

PAGAILA REZA A

Semiconductor device and method of forming vertical interconnect structure using stud bumps

AGILENT TECHNOLOGIES INC

High temperature flip chip joining flux that obviates the cleaning process

NAT SEMICONDUCTOR CORP

Stress reduction package and process

STATS CHIPPAC PTE LTD

Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits