Inventor

TAGUCHI MASAO

JP115 patents

⚠️ This page may combine multiple inventors who share the name “TAGUCHI MASAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAGUCHI MASAO

FUJITSU LTD

Three-dimensional integrated circuit and manufacturing method thereof

Semiconductor memory device for operating in synchronization with edge of clock signal

Dynamic memory circuit with automatic refresh function

Semiconductor device and semiconductor system for high-speed data transfer

Variable delay circuit and semiconductor integrated circuit device

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Semiconductor memory device having a refresh operation

Memory subsystem operated in synchronism with a clock

Signal transmission with reduced ringing of signals

Semiconductor device, semiconductor system, and digital delay circuit

Semiconductor device, semiconductor system, and digital delay circuit

Semiconductor integrated circuit memory

Semiconductor device using complementary clock and signal input state detection circuit used for the same

Semiconductor memory device

System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor

Electronic circuit apparatus for transmitting signals through a bus and semiconductor device for generating a predetermined stable voltage

Bus configuration and input/output buffer

Reference voltage generating circuit having step-down circuit outputting a voltage equal to a reference voltage

Termination circuits and related output buffers

Optical exposure method

Semiconductor memory device having a testing function and method of testing the same

Method of producing a dynamic random access memory device

Dynamic random access memory device and method of producing same

Mask, mask producing method and pattern forming method using mask

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Semiconductor device and multichip module

Bus configuration and input/output buffer

Reference voltage generation circuit using source followers

Reference voltage generation circuit using source followers

LSI device with memory and logics mounted thereon

Signal transmission with reduced ringing of signals

Termination circuits and related output buffers

Bus configuration and input/output buffer

Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data

Semiconductor device capable of selecting operation mode based on clock frequency

Reference voltage generation circuit

Voltage generator for a semiconductor integrated circuit

On-chip voltage regulator and semiconductor memory device using the same

Method of making a dram cell with stacked capacitor

Semiconductor memory device and method for producing the same

Semiconductor device having a superconductive wiring

Dynamic random access memory trench capacitor

Dynamic random access memory having trench capacitor with polysilicon lined lower electrode

Method and device for refreshing dynamic semiconductor memory device

Semiconductor memory device

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Input/output data synchronizing device

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

ELPIDA MEMORY INC

Nonvolatile semiconductor memory device and method of reading data from nonvolatile semiconductor memory device