Inventor

KFIR AVIV

IL59 patents

⚠️ This page may combine multiple inventors who share the name “KFIR AVIV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KFIR AVIV

MELLANOX TECH TLV LTD

Using consistent hashing for ECMP routing

Enhanced traffic distribution using VRF tables

Network switch operating as packet generator

Efficient parsing of optional header fields

Direct memory access (DMA) engine for diagnostic data

Global policers

Systems and methods for distributed storage of data across multiple hash tables

Listing congestion notification packet generation by switch

Transaction based scheduling

Burst score

Mirroring dropped packets

Reusing switch ports for external buffer network

Deduplication of mirror traffic in analyzer aggregation network

Scaling of switching tables with high bandwidth

Longest prefix match using a binary search tree with compressed hash tables

Power-efficient activation of multi-lane ports in a network element

Using consistent hashing for ECMP routing

Multi-chassis link aggregation learning on standard ethernet links

Combined pause-resume and credit-based flow-control

Rate limiting in a multi-chassis environment by exchanging information between peer network elements

Hash table-based mask length computation for longest prefix match caching

Field checking based caching of ACL lookups to ease ACL lookup search

Jump on a match optimization for longest prefix match using a binary search tree

Fast rerouting using egress-port loopback

Network element with congestion-aware match tables

IP route caching with two search stages on prefix length

Telemetry event aggregation

Hardware acceleration for uploading/downloading databases

Efficient parsing of extended packet headers

TCAM with multi region lookups and a single logical lookup

Efficient caching of TCAM rules in RAM

MELLANOX TECHNOLOGIES LTD

Routing via multiple paths with efficient traffic distribution

Network high availability using temporary re-routing

Efficient memory utilization for cartesian products of rules

Efficient implementation of MPLS tables for multi-level and multi-path scenarios

Efficient parsing tuned to prevalent packet types

Efficient memory utilization for cartesian products of rules

Dynamically reserved resource allocation

Queue bandwidth estimation for management of shared buffers and allowing visibility of shared buffer status

Global policers

Early and efficient packet truncation

Dynamically reserved resource allocation

Optimizing header-based action selection

End-to-end flow control with intermediate media access control security devices

Gateway for remote direct memory access over converged ethernet

Adaptive port routing

Low-latency delivery of in-band telemetry data

Latency detection using multiple clocks, including determination of whether latency exceeds a threshold

Parsing using null header node

NVIDIA CORP

Hardware latency monitoring for memory device input/output requests