Inventor
NOWATZYK ANDREAS
US31 patents
⚠️ This page may combine multiple inventors who share the name “NOWATZYK ANDREAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEWLETT PACKARD DEVELOPMENT CO
13 patentsUS6668308B2Dec 23, 2003
Scalable architecture based on single-chip multiprocessing
HEWLETT PACKARD DEVELOPMENT CO223 citations99
US6988170B2Jan 17, 2006
Scalable architecture based on single-chip multiprocessing
HEWLETT PACKARD DEVELOPMENT CO97 citations98
US6725334B2Apr 20, 2004
Method and system for exclusive two-level caching in a chip-multiprocessor
HEWLETT PACKARD DEVELOPMENT CO118 citations98
US6697919B2Feb 24, 2004
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO108 citations97
US6675265B2Jan 6, 2004
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
HEWLETT PACKARD DEVELOPMENT CO93 citations97
US6636949B2Oct 21, 2003
System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
HEWLETT PACKARD DEVELOPMENT CO80 citations97
US6622217B2Sep 16, 2003
Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO114 citations97
US6725343B2Apr 20, 2004
System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO61 citations96
US6751720B2Jun 15, 2004
Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy
HEWLETT PACKARD DEVELOPMENT CO42 citations91
US7389389B2Jun 17, 2008
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO12 citations84
US7123211B2Oct 17, 2006
Surround-vision display system
HEWLETT PACKARD DEVELOPMENT CO12 citations84
US6925537B2Aug 2, 2005
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
HEWLETT PACKARD DEVELOPMENT CO11 citations73
US6912624B2Jun 28, 2005
Method and system for exclusive two-level caching in a chip-multiprocessor
HEWLETT PACKARD DEVELOPMENT CO4 citations63
VMWARE INC
9 patentsUS11544194B1Jan 3, 2023
Coherence-based cache-line Copy-on-Write
VMWARE INC3 citations73
US11442865B1Sep 13, 2022
Smart prefetching for remote memory
VMWARE INC2 citations72
US12147528B2Nov 19, 2024
Coherence-based attack detection
VMWARE INC0 citations62
US12008361B2Jun 11, 2024
Coherence-based dynamic code rewriting, tracing and code coverage
VMWARE INC0 citations62
US11620192B2Apr 4, 2023
Hardware-assisted memory disaggregation with recovery from network failures using non-volatile memory
VMWARE INC1 citations62
US12019554B2Jun 25, 2024
Smart prefetching for remote memory
VMWARE INC0 citations61
US11586545B2Feb 21, 2023
Smart prefetching for remote memory
VMWARE INC0 citations61
US11880309B2Jan 23, 2024
Method and system for tracking state of cache lines
VMWARE INC0 citations47
US11782832B2Oct 10, 2023
Low latency host processor to coherent device interaction
VMWARE INC0 citations47
NOWATZYK ANDREAS
3 patentsSUN MICROSYSTEMS INC
3 patentsUS6128702AOct 3, 2000
Integrated processor/memory device with victim data cache
SUN MICROSYSTEMS INC45 citations96
US5900011AMay 4, 1999
Integrated processor/memory device with victim data cache
SUN MICROSYSTEMS INC61 citations96
US6199142B1Mar 6, 2001
Processor/memory device with integrated CPU, main memory, and full width cache and associated method
SUN MICROSYSTEMS INC49 citations92