Inventor
APPUSWAMY RATHINAKUMAR
US42 patents
Patents
42 patentsUS10621489B2Apr 14, 2020
Massively parallel neural inference computing elements
IBM30 citations94
US11138495B2Oct 5, 2021
Classifying features using a neurosynaptic system
IBM6 citations84
US10558892B2Feb 11, 2020
Scene understanding using a neurosynaptic system
IBM3 citations84
US10318862B2Jun 11, 2019
Transform for a neurosynaptic core circuit
IBM3 citations84
US10204301B2Feb 12, 2019
Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrate
IBM8 citations84
US10043110B2Aug 7, 2018
Scene understanding using a neurosynaptic system
IBM5 citations84
US10019667B2Jul 10, 2018
Transform for a neurosynaptic core circuit
IBM5 citations84
US9971965B2May 15, 2018
Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm
IBM14 citations84
US9798972B2Oct 24, 2017
Feature extraction using a neurosynaptic system for object classification
IBM19 citations84
US9536179B2Jan 3, 2017
Scene understanding using a neurosynaptic system
IBM7 citations84
US9412063B2Aug 9, 2016
Transform architecture for multiple neurosynaptic core circuits
IBM13 citations84
US9406015B2Aug 2, 2016
Transform for a neurosynaptic core circuit
IBM4 citations84
US9373058B2Jun 21, 2016
Scene understanding using a neurosynaptic system
IBM9 citations84
US12387082B2Aug 12, 2025
Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit
IBM2 citations74
US11501140B2Nov 15, 2022
Runtime reconfigurable neural network processor core
IBM2 citations73
US10650301B2May 12, 2020
Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
IBM2 citations73
US10140551B2Nov 27, 2018
Scene understanding using a neurosynaptic system
IBM2 citations73
US10115054B2Oct 30, 2018
Classifying features using a neurosynaptic system
IBM2 citations73
US11270196B2Mar 8, 2022
Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine
IBM2 citations71
US11537859B2Dec 27, 2022
Flexible precision neural inference processing unit
IBM3 citations70
US12182687B2Dec 31, 2024
Data representation for dynamic precision in neural network cores
IBM1 citations62
US12165050B2Dec 10, 2024
Networks for distributing parameters and data to neural network compute cores
IBM0 citations62
US12056598B2Aug 6, 2024
Runtime reconfigurable neural network processor core
IBM0 citations62
US11663461B2May 30, 2023
Instruction distribution in an array of neural network cores
IBM0 citations62
US11238347B2Feb 1, 2022
Data distribution in an array of neural network cores
IBM1 citations62
US11010662B2May 18, 2021
Massively parallel neural inference computing elements
IBM0 citations62
US10832125B2Nov 10, 2020
Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm
IBM1 citations62
US12406186B2Sep 2, 2025
Conflict-free, stall-free, broadcast network on chip
IBM1 citations60
US12481861B2Nov 25, 2025
Hierarchical parallelism in a network of distributed neural network cores
IBM0 citations52
US12067472B2Aug 20, 2024
Defect resistant designs for location-sensitive neural network processor arrays
IBM0 citations52
US11847553B2Dec 19, 2023
Parallel computational architecture with reconfigurable core-level and vector-level parallelism
IBM0 citations52
US10846567B2Nov 24, 2020
Scene understanding using a neurosynaptic system
IBM0 citations52
US10832121B2Nov 10, 2020
Transform for a neurosynaptic core circuit
IBM0 citations52
US10755166B2Aug 25, 2020
Transform architecture for multiple neurosynaptic core circuits
IBM0 citations52
US10198690B2Feb 5, 2019
Transform architecture for multiple neurosynaptic core circuits
IBM0 citations52
US10198688B2Feb 5, 2019
Transform for a neurosynaptic core circuit
IBM0 citations52
US12443830B2Oct 14, 2025
Compressed weight distribution in networks of neural processors
IBM0 citations51
US11263011B2Mar 1, 2022
Compound instruction set architecture for a neural inference chip
IBM0 citations51
US12554978B2Feb 17, 2026
Horizontal and vertical assertions for validation of neuromorphic hardware
IBM0 citations48
US12400112B2Aug 26, 2025
Efficient method for VLSI implementation of useful neural network activation functions
IBM0 citations47
US11636317B2Apr 25, 2023
Long-short term memory (LSTM) cells on spiking neuromorphic hardware
IBM0 citations47
US11823054B2Nov 21, 2023
Learned step size quantization
IBM0 citations45