Inventor

DATTA PALLAB

US63 patents

⚠️ This page may combine multiple inventors who share the name “DATTA PALLAB”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DATTA PALLAB

IBM

Massively parallel neural inference computing elements

Hardware architecture for simulating a neural network of neurons

Scheduler and simulator for an area-efficient, reconfigurable, energy-efficient, speed-efficient neural network

Scene understanding using a neurosynaptic system

Fault-tolerant power-driven synthesis

Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrate

Scene understanding using a neurosynaptic system

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Scene understanding using a neurosynaptic system

Scene understanding using a neurosynaptic system

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Mapping of algorithms to neurosynaptic hardware

Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit

Runtime reconfigurable neural network processor core

Graph partitioning and placement for multi-chip neurosynaptic networks

Power-driven synthesis under latency constraints

Optimizing core utilization in neurosynaptic systems

Hardware architecture for simulating a neural network of neurons

Scene understanding using a neurosynaptic system

Compositional prototypes for scalable neurosynaptic networks

Mapping graphs onto core-based neuromorphic architectures

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Core utilization optimization by dividing computational blocks across cores

Optimizing neurosynaptic networks

Flexible precision neural inference processing unit

Core utilization optimization by dividing computational blocks across cores

Hardware architecture for simulating a neural network of neurons

Mapping graphs onto core-based neuromorphic architectures

Power driven synaptic network synthesis

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Data representation for dynamic precision in neural network cores

Networks for distributing parameters and data to neural network compute cores

Runtime reconfigurable neural network processor core

Instruction distribution in an array of neural network cores

Distributed, event-based computation using neuromorphic cores

Fault-tolerant power-driven synthesis

Data distribution in an array of neural network cores

Hardware-software co-design of neurosynaptic systems

Compositional prototypes for scalable neurosynaptic networks

Massively parallel neural inference computing elements

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Conflict-free, stall-free, broadcast network on chip

Neural network weight distribution from a grid of memory elements

Block transfer of neuron output values through data memory for neurosynaptic processors

Hierarchical parallelism in a network of distributed neural network cores

Functional synthesis of networks of neurosynaptic cores on neuromorphic substrates

Automatic timing resolution among neural network components

Defect resistant designs for location-sensitive neural network processor arrays

DATTA PALLAB

Multi-processor cortical simulations with reciprocal connections with shared weights