Inventor

FLICKNER MYRON D

US57 patents

⚠️ This page may combine multiple inventors who share the name “FLICKNER MYRON D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FLICKNER MYRON D

IBM

Portable device-based shopping checkout

Massively parallel neural inference computing elements

Method of detecting and tracking groups of people

Automated visual inspection of electronic component leads prior to placement

Apparatus and method for computing the radon transform of digital images

Method and means for efficiently handling boundary conditions in connected component labeling

Fault-tolerant power-driven synthesis

Transform for a neurosynaptic core circuit

Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrate

Transform for a neurosynaptic core circuit

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Transform architecture for multiple neurosynaptic core circuits

Transform for a neurosynaptic core circuit

Mapping of algorithms to neurosynaptic hardware

Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit

Runtime reconfigurable neural network processor core

Graph partitioning and placement for multi-chip neurosynaptic networks

Power-driven synthesis under latency constraints

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Flexible precision neural inference processing unit

Power driven synaptic network synthesis

Alarm solution for securing shopping checkout

Data representation for dynamic precision in neural network cores

Networks for distributing parameters and data to neural network compute cores

Runtime reconfigurable neural network processor core

Instruction distribution in an array of neural network cores

Fault-tolerant power-driven synthesis

Data distribution in an array of neural network cores

Hardware-software co-design of neurosynaptic systems

Distributed state via cascades of tensor decompositions and neuron activation binding on neuromorphic hardware

Massively parallel neural inference computing elements

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Converting digital numeric data to spike event data

Low energy deep-learning networks for generating auditory features for audio processing pipelines

High-frame-rate real-time multiscale spatiotemporal disparity on distributed low-power event-based neuromorphic hardware

Hierarchical parallelism in a network of distributed neural network cores

Functional synthesis of networks of neurosynaptic cores on neuromorphic substrates

Automatic timing resolution among neural network components

Defect resistant designs for location-sensitive neural network processor arrays

Parallel computational architecture with reconfigurable core-level and vector-level parallelism

Transform for a neurosynaptic core circuit

Converting spike event data to digital numeric data

Transform architecture for multiple neurosynaptic core circuits

CONNELL II JONATHAN H

Smart scanning system

Customer rewarding

Visual security for point of sale terminals

Controlling shopper checkout throughput

Method, system, and program product for determining a state of a shopping receptacle