Inventor

SAWADA JUN

US72 patents

⚠️ This page may combine multiple inventors who share the name “SAWADA JUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAWADA JUN

IBM

Massively parallel neural inference computing elements

Method and apparatus for performing rotate operations using cascaded multiplexers

Yield tolerance in a neurosynaptic system

Scaling multi-core neurosynaptic networks across chip boundaries

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Self-timed, event-driven neurosynaptic core controller

Array of processor core circuits with reversible tiers

Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs

Replaceable sequenced one-time pads for detection of cloned service client

Dual deterministic and stochastic neurosynaptic core circuit

Dual deterministic and stochastic neurosynaptic core circuit

Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit

Fused booth encoder multiplexer

Runtime reconfigurable neural network processor core

Performing error detection during deterministic program execution

Scaling multi-core neurosynaptic networks across chip boundaries

Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

Yield tolerance in a neurosynaptic system

Peripheral device interconnections for neurosynaptic systems

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Memory-mapped interface for message passing computing systems

Flexible precision neural inference processing unit

Yield tolerance in a neurosynaptic system

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Data representation for dynamic precision in neural network cores

Networks for distributing parameters and data to neural network compute cores

Runtime reconfigurable neural network processor core

Instruction distribution in an array of neural network cores

Data distribution in an array of neural network cores

Massively parallel neural inference computing elements

Peripheral device interconnections for neurosynaptic systems

Dual deterministic and stochastic neurosynaptic core circuit

Converting digital numeric data to spike event data

Scanning latches using selecting array

Conflict-free, stall-free, broadcast network on chip

Neural network weight distribution from a grid of memory elements

Block transfer of neuron output values through data memory for neurosynaptic processors

TOKYO ELECTRIC POWER CO

Apparatus for tracking an overhead line and automatically moving around obstacles on the line

Suspension-type line arrester

CATALER CORP

Exhaust gas purification catalyst

BAUMGARTNER JASON R

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

SAWADA JUN

Verifying the error bound of numerical computation implemented in computer systems

HONDA MOTOR CO LTD

Pressure distribution measurement system

SUMITOMO RUBBER IND

Rotaxane and polyurethane using the same

BELLUOMINI WENDY ANN

Fused booth encoder multiplexer

PARUTHI VIRESH

Verifying data intensive state transition machines related application