Inventor

TSAI MING-HSING

TW118 patents

⚠️ This page may combine multiple inventors who share the name “TSAI MING-HSING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI MING-HSING

TAIWAN SEMICONDUCTOR MFG

Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology

Method to improve planarity of electroplated copper

Poly resistor structure for damascene metal gate

Method of improved copper gap fill

Self aligned dual damascene process and structure with low parasitic capacitance

Method for improvement of gap filling capability of electrochemical deposition of copper

Method to solve via poisoning for porous low-k dielectric

Selective growth of copper for advanced metallization

Method of forming bumps for flip chip applications

Multi-step electrochemical copper deposition process with improved filling capability

Gap filling by two-step plating

Method of forming dual damascene structure

Method for preventing seed layer oxidation for high aspect gap fill

Method for marking a wafer without inducing flat edge particle problem

Semiconductor device and fabrication method thereof

Reduction of Cu line damage by two-step CMP

Method for forming a copper damascene structure over tungsten plugs with improved adhesion, oxidation resistance, and diffusion barrier properties using nitridation of the tungsten plug

Fabrication process for low resistivity tungsten layer with good adhesion to insulator layers

Method of doping copper metallization

Interconnects with harmonized stress and methods for fabricating the same

Method and apparatus for electroplating

Method for forming dual damascene structures with tapered via portions and improved performance

Method for improving an electrodeposition process through use of a multi-electrode assembly

Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers

Metal interconnect features with a doping gradient

Method to solve via poisoning for porous low-k dielectric

Method for fabricating metal gates in deep sub-micron devices

Method for integrating an electrodeposition and electro-mechanical polishing process

Copper back-end-of-line by electropolish

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

Ammonium fluoride pre-clean protection

Methods for pre-deposition treatment of a work-function metal layer

Method of forming a contact with a silicide region

Conductive feature formation and structure

Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby

Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby

Chemical direct pattern plating method

Contact conductive feature formation and structure

Semiconductor device and method

Contact conductive feature formation and structure

Contact structure and the method of forming the same

Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

Semiconductor device and method

Method of making a silicide beneath a vertical structure

Systems and methods for integrated resputtering in a physical vapor deposition chamber

Vertical structure having an etch stop over portion of the source

Semiconductor device pre-cleaning

Conductive feature formation and structure using bottom-up filling deposition

CHEN CHIEN-AN

Mechanisms of forming damascene interconnect structures

UNITED MICROELECTRONICS CORP

Process for fabricating tantalum nitride diffusion barrier for copper matallization