Inventor

FRATIN LORENZO

IT73 patents

⚠️ This page may combine multiple inventors who share the name “FRATIN LORENZO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FRATIN LORENZO

MICRON TECHNOLOGY INC

Three-dimensional memory array

Self-selecting memory array with horizontal bit lines

Three dimensional memory arrays

Apparatuses including multi-level memory cells and methods of operation of same

Self-selecting memory cell with dielectric barrier

Memory arrays and methods of forming memory cells

Cross point array architecture for multiple decks

Word line structures for three-dimensional memory arrays

Decoding architecture for memory devices

Apparatuses including multi-level memory cells and methods of operation of same

Techniques for forming self-aligned memory structures

Three-dimensional memory array

Three dimensional memory arrays

Memory device with a split pillar architecture

Memory array with graded memory stack resistances

Chalcogenide memory device components and composition

Memory device and method for manufacturing the same

Memory devices having one-time-programmable fuses and/or antifuses formed from thin-film transistors

Techniques for forming self-aligned memory structures

Split pillar architectures for memory devices

Memory device with a split pillar architecture

Decoding for a memory device

Three-dimensional memory array

Decoding for a memory device

Memory array with graded memory stack resistances

Decoding for a memory device

Decoding for a memory device

Split pillar architectures for memory devices

Self-selecting memory cell with dielectric barrier

Decoding architecture for memory devices

Accessing memory cells in a vertical memory array

Word line structures for three-dimensional memory arrays

Memory cells with sidewall and bulk regions in vertical structures

Memory array having air gaps

Self-selecting memory array with horizontal access lines

Architecture of three-dimensional memory device and methods regarding the same

Chalcogenide memory device compositions

Memory cells with sidewall and bulk regions in vertical structures

Decoding architecture for word line tiles

Decoding architecture for memory devices

Memory device with laterally formed memory cells

Memory cells with sidewall and bulk regions in planar structures

Apparatuses including multi-level memory cells and methods of operation of same

SGS THOMSON MICROELECTRONICS

High-voltage-resistant MOS transistor, and corresponding manufacturing process

Nonvolatile memory cell and a method for forming the same

Method of making asymmetric nonvolatile memory cell

Method of producing MOSFET transistors by means of tilted implants

PELLIZZER FABIO

Memory arrays and methods of forming memory cells

INTEL CORP

Non-volatile memory cell structures including a chalcogenide material having a narrowed end and a three-dimensional memory device

ST MICROELECTRONICS SRL

Flash EEPROM with integrated device for limiting the erase source voltage