Inventor

HU YU-HSIANG

TW181 patents

⚠️ This page may combine multiple inventors who share the name “HU YU-HSIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HU YU-HSIANG

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming semiconductor packages having through package vias

Semiconductor structure and method of forming

Advanced structure for info wafer warpage reduction

Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region

Semiconductor device and method of manufacture

Chip package and method of forming the same

Sensing die encapsulated by an encapsulant with a roughness surface having a hollow region

Sensing component encapsulated by an encapsulant with a roughness surface having a hollow region

Semiconductor package and method of forming the same

Integrated fan-out package and manufacturing method thereof

Semiconductor package and method

Semiconductor package and method of forming the same

Semiconductor device and method

Package structure and method of manufacturing the same

Integrated fan-out package and method of fabricating the same

Semiconductor structure and method of forming

Planarizing RDLs in RDL-first processes through CMP process

Info structure and method forming same

Semicondcutor device package and method of forming semicondcutor device package

Semiconductor structure and method of forming

Package and manufacturing method thereof

Integrated fan-out package

Fan-out interconnect structure and methods forming the same

Semiconductor device and method

Semiconductor device and method of manufacturing the same

Die and package structure

Composition for sacrificial film, package, manufacturing method of package

Semiconductor package and methods of forming the same

Integrated fan-out package and manufacturing method thereof

Package structure and method of fabricating the same

Integrated circuit packages having adhesion layers for through vias

Stacked via structure

Package structure comprising buffer layer for reducing thermal stress and method of forming the same

Redistribution structure for semiconductor device and method of forming same

Semiconductor package and method

Lithography

Polymer layer in semiconductor device and method of manufacture

Semiconductor package and method of forming the same

Chip package and method of forming the same

Semiconductor package and method

Semiconductor package

Planarizing RDLS in RDL-first processes through CMP process

Package structure and method of manufacturing the same

Package structure comprising buffer layer for reducing thermal stress and method of forming the same

Method of manufacturing semiconductor structure

Method of forming semiconductor device

Package structure and method of forming the same

Wafer chuck

TAIWAN SEMICONDUCTOR MFG

Integrated structure in wafer level package

IMEC

Method for bonding semiconductor substrates and devices obtained thereof