Inventor
CHINYA GAUTHAM
US36 patents
⚠️ This page may combine multiple inventors who share the name “CHINYA GAUTHAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS9990206B2Jun 5, 2018
Mechanism for instruction set based thread execution of a plurality of instruction sequencers
INTEL CORP8 citations82
US7768518B2Aug 3, 2010
Enabling multiple instruction stream/multiple data stream extensions on microprocessors
INTEL CORP19 citations82
US8028295B2Sep 27, 2011
Apparatus, system, and method for persistent user-level thread
INTEL CORP4 citations74
US12141683B2Nov 12, 2024
Performance scaling for dataflow deep neural network hardware accelerators
INTEL CORP3 citations70
US10867142B2Dec 15, 2020
Multiplication-free approximation for neural networks and sparse coding
INTEL CORP2 citations70
US9459874B2Oct 4, 2016
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
INTEL CORP1 citations62
US7631125B2Dec 8, 2009
Dynamically migrating channels
INTEL CORP2 citations62
US12438553B2Oct 7, 2025
Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors
INTEL CORP0 citations61
US12288153B2Apr 29, 2025
Schedule-aware tensor distribution module
INTEL CORP0 citations61
US11907827B2Feb 20, 2024
Schedule-aware tensor distribution module
INTEL CORP0 citations61
US11804851B2Oct 31, 2023
Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors
INTEL CORP0 citations61
US12242861B2Mar 4, 2025
Methods and apparatus to load data within a machine learning accelerator
INTEL CORP0 citations60
US11922178B2Mar 5, 2024
Methods and apparatus to load data within a machine learning accelerator
INTEL CORP1 citations60
US11714977B2Aug 1, 2023
Multiplication-free approximation for neural networks and sparse coding
INTEL CORP0 citations60
US11232273B2Jan 25, 2022
Multiplication-free approximation for neural networks and sparse coding
INTEL CORP0 citations60
US12386618B2Aug 12, 2025
Multi-buffered register files with shared access circuits
INTEL CORP0 citations59
US9875102B2Jan 23, 2018
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9766891B2Sep 19, 2017
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9588771B2Mar 7, 2017
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
INTEL CORP1 citations52
US9383997B2Jul 5, 2016
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US8001364B2Aug 16, 2011
Dynamically migrating channels
INTEL CORP0 citations52
US12554962B2Feb 17, 2026
Configurable processor element arrays for implementing convolutional neural networks
INTEL CORP0 citations50
WANG HONG
4 patentsUS8719819B2May 6, 2014
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
WANG HONG4 citations83
US8914618B2Dec 16, 2014
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
WANG HONG3 citations62
US8074274B2Dec 6, 2011
User-level privilege management
WANG HONG3 citations62
US9720697B2Aug 1, 2017
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
WANG HONG0 citations51
CHINYA GAUTHAM
4 patentsUS8516483B2Aug 20, 2013
Transparent support for operating system services for a sequestered sequencer
CHINYA GAUTHAM10 citations83
US8479217B2Jul 2, 2013
Apparatus, system, and method for persistent user-level thread
CHINYA GAUTHAM7 citations83
US8214574B2Jul 3, 2012
Event handling for architectural events at high privilege levels
CHINYA GAUTHAM4 citations61
US8296552B2Oct 23, 2012
Dynamically migrating channels
CHINYA GAUTHAM0 citations51