Inventor
MOHAPATRA DEBABRATA
US14 patents
⚠️ This page may combine multiple inventors who share the name “MOHAPATRA DEBABRATA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
13 patentsUS12141683B2Nov 12, 2024
Performance scaling for dataflow deep neural network hardware accelerators
INTEL CORP3 citations70
US12438553B2Oct 7, 2025
Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors
INTEL CORP0 citations61
US12288153B2Apr 29, 2025
Schedule-aware tensor distribution module
INTEL CORP0 citations61
US11907827B2Feb 20, 2024
Schedule-aware tensor distribution module
INTEL CORP0 citations61
US11804851B2Oct 31, 2023
Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors
INTEL CORP0 citations61
US12242861B2Mar 4, 2025
Methods and apparatus to load data within a machine learning accelerator
INTEL CORP0 citations60
US11922178B2Mar 5, 2024
Methods and apparatus to load data within a machine learning accelerator
INTEL CORP1 citations60
US12386618B2Aug 12, 2025
Multi-buffered register files with shared access circuits
INTEL CORP0 citations59
US12229673B2Feb 18, 2025
Sparsity-aware datastore for inference processing in deep neural network architectures
INTEL CORP0 citations58
US12147836B2Nov 19, 2024
Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators
INTEL CORP1 citations58
US12554962B2Feb 17, 2026
Configurable processor element arrays for implementing convolutional neural networks
INTEL CORP0 citations50
US11010166B2May 18, 2021
Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits
INTEL CORP0 citations50
US12367380B2Jul 22, 2025
System and method for balancing sparsity in weights for accelerating deep neural networks
INTEL CORP0 citations43