P

Inventor

BRICK CORMAC

US24 patents
⚠️ This page may combine multiple inventors who share the name “BRICK CORMAC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

16 patents
US11940907B2Mar 26, 2024

Methods and apparatus for sparse tensor storage for neural network accelerators

INTEL CORP3 citations72
US12141683B2Nov 12, 2024

Performance scaling for dataflow deep neural network hardware accelerators

INTEL CORP3 citations70
US12438553B2Oct 7, 2025

Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors

INTEL CORP0 citations61
US12288153B2Apr 29, 2025

Schedule-aware tensor distribution module

INTEL CORP0 citations61
US11907827B2Feb 20, 2024

Schedule-aware tensor distribution module

INTEL CORP0 citations61
US11804851B2Oct 31, 2023

Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors

INTEL CORP0 citations61
US12430239B2Sep 30, 2025

Methods and apparatus for sparse tensor storage for neural network accelerators

INTEL CORP0 citations60
US12242861B2Mar 4, 2025

Methods and apparatus to load data within a machine learning accelerator

INTEL CORP0 citations60
US12169643B2Dec 17, 2024

Methods, apparatus, and articles of manufacture to increase data reuse for multiply and accumulate (MAC) operations

INTEL CORP0 citations60
US11922178B2Mar 5, 2024

Methods and apparatus to load data within a machine learning accelerator

INTEL CORP1 citations60
US11789646B2Oct 17, 2023

Methods, apparatus, and articles of manufacture to increase data reuse for multiply and accumulate (MAC) operations

INTEL CORP0 citations60
US12229673B2Feb 18, 2025

Sparsity-aware datastore for inference processing in deep neural network architectures

INTEL CORP0 citations58
US12147836B2Nov 19, 2024

Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators

INTEL CORP1 citations58
US12554962B2Feb 17, 2026

Configurable processor element arrays for implementing convolutional neural networks

INTEL CORP0 citations50
US11347828B2May 31, 2022

Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication

INTEL CORP0 citations50
US12124941B2Oct 22, 2024

Methods and apparatus for dynamic batching of data for neural network workloads

INTEL CORP0 citations39

MOVIDIUS LTD

4 patents

LINEAR ALGEBRA TECH LIMITED

2 patents

LINEAR ALGEBRA TECHNOLOGIES LTD

1 patent

LINEAR ALGEBRA TECH LTD

1 patent