Inventor
IKETANI SHINICHI
US28 patents
⚠️ This page may combine multiple inventors who share the name “IKETANI SHINICHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SANMINA CORP
20 patentsUS9781830B2Oct 3, 2017
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP11 citations82
US9781844B2Oct 3, 2017
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP5 citations82
US10201085B2Feb 5, 2019
Methods of forming blind vias for printed circuit boards
SANMINA CORP4 citations72
US11399439B2Jul 26, 2022
Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board
SANMINA CORP2 citations70
US10188001B2Jan 22, 2019
Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board
SANMINA CORP3 citations70
US10820427B2Oct 27, 2020
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP4 citations69
US10993333B2Apr 27, 2021
Methods of manufacturing ultra thin dielectric printed circuit boards with thin laminates
SANMINA CORP0 citations62
US12150254B2Nov 19, 2024
Method of forming a laminate structure having a plated through-hole using a removable cover layer
SANMINA CORP0 citations61
US11765827B2Sep 19, 2023
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP0 citations61
US11246226B2Feb 8, 2022
Laminate structures with hole plugs and methods of forming laminate structures with hole plugs
SANMINA CORP0 citations61
US12575036B2Mar 10, 2026
Method of forming high aspect ratio plated through holes
SANMINA CORP0 citations60
US11304311B2Apr 12, 2022
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP0 citations59
US10757819B2Aug 25, 2020
Method of forming a laminate structure having a plated through-hole using a removable cover layer
SANMINA CORP0 citations51
US10362687B2Jul 23, 2019
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP0 citations51
US10237983B2Mar 19, 2019
Method for forming hole plug
SANMINA CORP0 citations51
US10123432B2Nov 6, 2018
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP0 citations51
US10667390B2May 26, 2020
Simultaneous and selective wide gap partitioning of via structures using plating resist
SANMINA CORP0 citations50
US10811210B2Oct 20, 2020
Multilayer printed circuit board via hole registration and accuracy
SANMINA CORP0 citations49
US10446356B2Oct 15, 2019
Multilayer printed circuit board via hole registration and accuracy
SANMINA CORP0 citations49
US9661758B2May 23, 2017
Methods of segmented through hole formation using dual diameter through hole edge trimming
SANMINA CORP0 citations49
AVERATEK CORP
8 patentsUS12548695B2Feb 10, 2026
Methods and devices for high resistance and low resistance conductor layers mitigating skin depth loss
AVERATEK CORP0 citations61
US11877404B2Jan 16, 2024
Catalyzed metal foil and uses thereof
AVERATEK CORP0 citations61
US11549184B2Jan 10, 2023
Coating of nano-scaled cavities
AVERATEK CORP0 citations60
US11142825B2Oct 12, 2021
Coating of nano-scaled cavities
AVERATEK CORP0 citations60
US11716819B2Aug 1, 2023
Asymmetrical electrolytic plating for a conductive pattern
AVERATEK CORP0 citations59
US12213258B2Jan 28, 2025
Method of manufacture for embedded IC chip directly connected to PCB
AVERATEK CORP0 citations57
US11076492B2Jul 27, 2021
Three dimensional circuit formation
AVERATEK CORP0 citations57
US12063748B2Aug 13, 2024
Catalyzed metal foil and uses thereof to produce electrical circuits
AVERATEK CORP0 citations44