Inventor

LESTER ROBERT ALLAN

US22 patents

⚠️ This page may combine multiple inventors who share the name “LESTER ROBERT ALLAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LESTER ROBERT ALLAN

COMPAQ COMPUTER CORP

System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system

Accelerated graphics port programmable memory access arbiter

Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device

Accelerated graphics port multiple entry gart cache allocation system and method

Accelerated graphics port memory mapped status and control registers

Accelerated Graphics Port two level Gart cache having distributed first level caches

System and method for dynamically allocating accelerated graphics port memory space

Generating an error signal when accessing an invalid memory page

Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus

Valid flag for disabling allocation of accelerated graphics port memory space

Direct memory access controller having programmable timing

Direct memory access controller having programmable timing

HEWLETT PACKARD DEVELOPMENT CO

Removable memory cartridge system for use with a server or other processor-based device

Removable memory cartridge system for use with a server or other processor-based device

Transaction generator for initialization, rebuild, and verify of memory

Removable memory cartridge system for use with a server or other processor-based device

Removable memory cartridge system for use with a server or other processor-based device

QUALCOMM INC

Independent power collapse methodology

Multi-mode instruction memory unit

COMPAQ INFORMATION TECHNOLOGIE

System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops

CODRESCU LUCIAN

System and method for generating and using predicates within a single instruction packet

SHEN JIAN

Buffer management structure with selective flush