Inventor
MASHIMOTO YOHKO
JP5 patents
Patents
5 patentsUS6020561AFeb 1, 2000
Printed circuit substrate with solder formed on pad-on-via and pad-off-via contacts thereof
INTEL CORP138 citations97
US6030854AFeb 29, 2000
Method for producing a multilayer interconnection structure
INTEL CORP60 citations93
US5660321AAug 26, 1997
Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts
INTEL CORP31 citations91
US5880530AMar 9, 1999
Multiregion solder interconnection structure
INTEL CORP31 citations90
US5811883ASep 22, 1998
Design for flip chip joint pad/LGA pad
INTEL CORP14 citations66