Inventor · disambiguated record
Kiyotake Sakurai
Also filed as: SAKURAI KIYOTAKE
10 granted patents·35 citations·filing 2010–2021
86Inventor score
Technology areasG11C
Top patents by PatentIndex Score
10 records- 0195US10056129B1Cell bottom node reset in a memory arrayMICRON TECHNOLOGY INC·Filed 2017·Granted Aug 21, 2018·17 cites·26 claims
- 0290US10229727B1Apparatus and method for controlling erasing data in ferroelectric memory cellsMICRON TECHNOLOGY INC·Filed 2018·Granted Mar 12, 2019·8 cites·31 claims
- 0386US10984848B2Apparatus and method for controlling erasing data in ferroelectric memory cellsMICRON TECHNOLOGY INC·Filed 2020·Granted Apr 20, 2021·2 cites·20 claims
- 0485US10685694B2Cell bottom node reset in memory arrayMICRON TECHNOLOGY INC·Filed 2019·Granted Jun 16, 2020·4 cites·20 claims
- 0581US10607678B2Apparatus and method for controlling erasing data in ferroelectric memory cellsMICRON TECHNOLOGY INC·Filed 2019·Granted Mar 31, 2020·3 cites·12 claims
- 0669US11742013B2Apparatus and method for controlling erasing data in ferroelectric memory cellsMICRON TECHNOLOGY INC·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 0768US11004492B2Cell bottom node reset in a memory arrayMICRON TECHNOLOGY INC·Filed 2020·Granted May 11, 2021·0 cites·20 claims
- 0867US10311933B2Cell bottom node reset in a memory arrayMICRON TECHNOLOGY INC·Filed 2018·Granted Jun 4, 2019·1 cites·20 claims
- 0941US10790004B2Apparatuses and methods for multi-bank and multi-pump refresh operationsMICRON TECHNOLOGY INC·Filed 2018·Granted Sep 29, 2020·0 cites·20 claims
- 1017US8238181B2Semiconductor device, circuit of controlling signal lines and method of controlling signal linesOGASAWARA TOMOHIRO·Filed 2010·Granted Aug 7, 2012·0 cites·16 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →