Inventor
VERGARI LOUIS PETER
3 patents
Patents
3 patentsUS4038642AJul 26, 1977
Input/output interface logic for concurrent operations
IBM70 citations92
US4053950AOct 11, 1977
Residual status reporting during chained cycle steal input/output operations
IBM27 citations78
US4038641AJul 26, 1977
Common polling logic for input/output interrupt or cycle steal data transfer requests
IBM19 citations68