Inventor
SCHERBININ SERGEY P
RU6 patents
⚠️ This page may combine multiple inventors who share the name “SCHERBININ SERGEY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
5 patentsUS10241801B2Mar 26, 2019
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator
INTEL CORP0 citations48
US10235171B2Mar 19, 2019
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor
INTEL CORP0 citations48
US10430191B2Oct 1, 2019
Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption
INTEL CORP0 citations42
US10241789B2Mar 26, 2019
Method to do control speculation on loads in a high performance strand-based loop accelerator
INTEL CORP0 citations37
US10241794B2Mar 26, 2019
Apparatus and methods to support counted loop exits in a multi-strand loop processor
INTEL CORP0 citations37