Inventor
GUTIERREZ III ERNESTO
GB10 patents
Patents
10 patentsUS10083926B1Sep 25, 2018
Stress relief solutions on WLCSP large/bulk copper plane design
DIALOG SEMICONDUCTOR UK LTD11 citations78
US11239185B2Feb 1, 2022
Embedded resistor-capacitor film for fan out wafer level packaging
DIALOG SEMICONDUCTOR UK LTD3 citations70
US10636742B2Apr 28, 2020
Very thin embedded trace substrate-system in package (SIP)
DIALOG SEMICONDUCTOR UK LTD4 citations70
US11075167B2Jul 27, 2021
Pillared cavity down MIS-SIP
DIALOG SEMICONDUCTOR UK LTD2 citations68
US10629507B1Apr 21, 2020
System in package (SIP)
DIALOG SEMICONDUCTOR UK LTD5 citations67
US12100674B2Sep 24, 2024
Embedded resistor-capacitor film for fan out wafer level packaging
DIALOG SEMICONDUCTOR UK LTD0 citations60
US11309255B2Apr 19, 2022
Very thin embedded trace substrate-system in package (SIP)
DIALOG SEMICONDUCTOR UK LTD0 citations59
US11114359B2Sep 7, 2021
Wafer level chip scale package structure
DIALOG SEMICONDUCTOR UK LTD1 citations59
US11532489B2Dec 20, 2022
Pillared cavity down MIS-SiP
DIALOG SEMICONDUCTOR UK LTD0 citations57
US10727174B2Jul 28, 2020
Integrated circuit package and a method for forming a wafer level chip scale package (WLCSP) with through mold via (TMV)
DIALOG SEMICONDUCTOR UK LTD0 citations38