Inventor
Suvarna Puneet Harischandra
US13 patents
Patents
13 patentsUS10510622B1Dec 17, 2019
Vertically stacked complementary-FET device with independent gate control
GLOBALFOUNDRIES INC46 citations97
US10304833B1May 28, 2019
Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
GLOBALFOUNDRIES INC19 citations86
US10418449B2Sep 17, 2019
Circuits based on complementary field-effect transistors
GLOBALFOUNDRIES INC14 citations85
US10784171B2Sep 22, 2020
Vertically stacked complementary-FET device with independent gate control
GLOBALFOUNDRIES INC7 citations84
US10236379B2Mar 19, 2019
Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process
GLOBALFOUNDRIES INC10 citations84
US10141414B1Nov 27, 2018
Negative capacitance matching in gate electrode structures
GLOBALFOUNDRIES INC12 citations83
US10497798B2Dec 3, 2019
Vertical field effect transistor with self-aligned contacts
GLOBALFOUNDRIES INC2 citations73
US10312154B2Jun 4, 2019
Method of forming vertical FinFET device having self-aligned contacts
GLOBALFOUNDRIES INC4 citations73
US10347745B2Jul 9, 2019
Methods of forming bottom and top source/drain regions on a vertical transistor device
GLOBALFOUNDRIES INC5 citations72
US9947789B1Apr 17, 2018
Vertical transistors stressed from various directions
GLOBALFOUNDRIES INC4 citations72
US10332969B2Jun 25, 2019
Negative capacitance matching in gate electrode structures
GLOBALFOUNDRIES INC1 citations62
US10446659B2Oct 15, 2019
Negative capacitance integration through a gate contact
GLOBALFOUNDRIES INC1 citations61
US10170617B2Jan 1, 2019
Vertical transport field effect transistors
GLOBALFOUNDRIES INC0 citations40