Inventor

SHEBANOW MICHAEL C

US45 patents

⚠️ This page may combine multiple inventors who share the name “SHEBANOW MICHAEL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEBANOW MICHAEL C

HAL COMPUTER SYSTEMS INC

Processor structure and method for maintaining and restoring precise state at any instruction boundary

Processor structure and method for a time-out checkpoint

Processor structure and method for tracking instruction status to maintain precise state

Processor structure and method for checkpointing instructions to maintain precise state

Processor structure and method for tracking floating-point exceptions

Processor structure and method for renamable trap-stack

Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation

Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state

Method and apparatus for coordinating the use of physical registers in a microprocessor

FUJITSU LTD

Structure and method for instruction boundary machine state restoration

Superscalar processor with multiple register windows and speculative return address generation

Addressing method for executing load instructions out of order with respect to store instructions

Method and apparatus for rotating active instructions in a parallel data processor

Method and apparatus for selecting the oldest queued instructions without data dependencies

Method for adjusting fetch program counter in response to the number of instructions fetched and issued

Programmable instruction trap system and method

Split data-flow scheduling mechanism

NVIDIA CORP

Atomic memory operators in a parallel processor

Instructions for managing a parallel cache hierarchy

Context switching using halt sequencing protocol

Halt context switching method and system

Unit status reporting protocol

Computing tessellation coordinates using dedicated hardware

Tree-based thread management

SHEBANOW MICHAEL C

Coverage caching

Address mapping for a parallel thread processor

Hardware warning protocol for processing units

Trap handler architecture for a parallel processing unit

Deferred complete virtual address computation for local memory space requests

ADVANCED MICRO DEVICES INC

Method and apparatus for error detection and correction in systems comprising floppy and/or hard disk drives

Method and apparatus for transferring data between a disk and a central processing unit

Method and apparatus for reading a disk

MOTOROLA INC

Data processor for performing simultaneous instruction retirement and backtracking

Randomly accessible memory having time overlapping memory accesses

RHOADES JOHNNY S

Distributing primitives to multiple rasterizers

Distributing primitives to multiple rasterizers

NICKOLLS JOHN R

Coalescing memory barrier operations across multiple parallel threads

Instructions for managing a parallel cache hierarchy

HAKURA ZIYAD S

Distributed stream output in a parallel processing unit

Distributed vertex attribute fetch

(unassigned)

Method and apparatus for register management using issue sequence prior physical register and register association validity information

LEGAKIS JUSTIN S

Computing tessellation coordinates using dedicated hardware

LINDHOLM JOHN ERIK

Method and system for connecting multiple shaders

FAR ALI TASDIGHI

Hybrid accumulation method in multiply-accumulate for machine learning

QIU XIAOGANG

Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict