Inventor

HOPPER DAWN M

US30 patents

⚠️ This page may combine multiple inventors who share the name “HOPPER DAWN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOPPER DAWN M

ADVANCED MICRO DEVICES INC

Process for fabricating an ONO structure having a silicon-rich silicon nitride layer

Use of sic for preventing copper contamination of low-k dielectric layers

Process for fabricating an ONO structure

Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics

Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers

Flash memory with controlled wordline width

Plasma etch process for nonhomogenous film

Use of sion for preventing copper contamination of dielectric layer

Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers

Semiconductor device with variable composition low-k inter-layer dielectric and method of making

Damascene processing using a silicon carbide hard mask

Method of fabricating dual damascene with silicon carbide via mask/ARC

Method for improving semiconductor dielectrics

HDP deposition hillock suppression method in integrated circuits

Process for fabricating high density memory cells using a polysilicon hard mask

Process for fabricating high density memory cells using a metallic hard mask

Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC

Low temperature hillock suppression method in integrated circuit interconnects

Hard mask removal process including isolation dielectric refill

Isolation trench fill process

Dual damascene with silicon carbide middle etch stop layer/ARC

Dielectric treatment in integrated circuit interconnects

Apparatus and method for manufacturing semiconductors using low dielectric constant materials

Damascene processing employing low Si-SiON etch stop layer/arc

Method for improving the dielectric constant of silicon-based semiconductor materials

Integration of an ion implant hard mask structure into a process for fabricating high density memory cells

Low dielectric constant etch stop layers in integrated circuit interconnects

Apparatus and method for manufacturing semiconductors using low dielectric constant materials

FASL LLC

Liner for semiconductor memories and manufacturing method therefor

CYPRESS SEMICONDUCTOR CORP

Programmable latency count to achieve higher memory bandwidth