Inventor

WOLLESEN DONALD L

US51 patents

⚠️ This page may combine multiple inventors who share the name “WOLLESEN DONALD L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOLLESEN DONALD L

ADVANCED MICRO DEVICES INC

Trench-gated vertical combination JFET and MOSFET devices

High conductivity interconnection line

Thin oxide anti-fuse

Junction profiling using a scanning voltage micrograph

Silicon-on-insulator configuration which is compatible with bulk CMOS architecture

Low capacitance interconnection

Short channel self-aligned VMOS field effect transistor

Field effect transistor with controlled body bias

Low capacitance interconnection

Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region

Non-volatile trench semiconductor device having a shallow drain region

Method of forming asymmetrically doped source/drain regions

On-chip transformers

Trench-gated vertical CMOS device

Method of manufacturing a raised source/drain MOSFET

Method of making a selective epitaxial growth circuit load element

Reduced electromigration interconnection line

Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask

Short channel self aligned VMOS field effect transistor

Method for manufacturing asymmetric channel transistor

Method for fabricating a trench-gated vertical CMOS device

Leaky lower interface for reduction of floating body effect in SOI devices

On-chip transformers

Short channel non-self aligned VMOS field effect transistor

Trenched gate metal oxide semiconductor device and method

Trenched gate non-volatile semiconductor device and method with corner doping and sidewall doping

Latchup-proof I/O circuit implementation

Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors

Method of forming asymmetrically doped source/drain regions

Non-volatile trench semiconductor device

Device analysis for face down chip

Double density V nonvolatile memory cell

Enhanced electromigration lifetime of metal interconnection lines

Switchable ESD protective shunting circuit for semiconductor devices

Use of fiducial marks for improved blank wafer defect review

Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings

Trenched gate metal oxide semiconductor device and method

Method for profiling semiconductor device junctions using a voltage contrast scanning electron microscope

Leaky lower interface for reduction of floating body effect in SOI devices

Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings

Fully recessed semiconductor method for low power applications with single wrap around buried drain region

Backside silicon removal for face down chip analysis

Polycide/poly diode SRAM load

Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors

Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors

Method and apparatus for determining the robustness of memory cells to induced soft errors using equivalent diodes

Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process

Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process

AMERICAN MICRO SYST

CMOS P-Well selective implant method

Notched cell ROM