Inventor

MAK PAK-KIN

US82 patents

⚠️ This page may combine multiple inventors who share the name “MAK PAK-KIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAK PAK-KIN

IBM

System serialization with early release of individual processor

SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum

Coherency management for a “switchless” distributed shared memory computer system

High speed remote storage controller

Resource arbitration system with resource checking and lockout avoidance

Multiprocessor serialization with early release of processors

Clustered computer system with deadlock avoidance

Method to determine retries for parallel ECC correction in a pipeline

Dynamic serialization of memory access in a multi-processor system

Interlock for controlling processor ownership of pipelined data for a store in cache

Disowning cache entries on aging out of the entry

Computer architecture incorporating processor clusters and hierarchical cache memories

Coherency management for a “switchless” distributed shared memory computer system

Bus protocol for a switchless distributed shared memory computer system

Method for deadlock avoidance in a cluster environment

Computer system deadlock request resolution using timed pulses

Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic

Memory management for a symmetric multiprocessor computer system

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

Nested cache coherency protocol in a tiered multi-node computer system

Nested cache coherency protocol in a tiered multi-node computer system

Computer system UE recovery logic

Processor memory array having memory macros for relocatable store protect keys

Separate data and coherency cache directories in a shared cache in a multiprocessor system

Method for ensuring system serialization (quiesce) in a multi-processor environment

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Hot cache line fairness arbitration in distributed modular SMP system

Hot cache line arbitration

Maintaining order with parallel access data streams

Memory controlled operations under dynamic relocation of storage

Non-disruptive clearing of varying address ranges from cache

Granting exclusive cache access using locality cache coherency state

Non-disruptive clearing of varying address ranges from cache

Non-disruptive clearing of varying address ranges from cache

Granting exclusive cache access using locality cache coherency state

Designated cache data backup during system operation

Target cache line arbitration within a processor cluster

Memory state indicator check operations

Memory state indicator check operations

Implementing an enhanced hover state with active prefetches

Topology for shared memory computer system

Preinstall of partial store cache lines

Non-data inclusive coherent (NIC) directory for cache

Non-data inclusive coherent (NIC) directory for cache

BLAKE MICHAEL A

Maintaining cache coherence in a multi-node, symmetric multiprocessing computer

Maintaining cache coherence in a multi-node, symmetric multiprocessing computer

CHECK MARK A

Memory error isolation and recovery in a multiprocessor computer system

BRONSON TIMOTHY C

Multilevel cache hierarchy for finding a cache line on a remote node

PAPAZOVA VESSELINA K

Cache coherency protocol with built in avoidance for conflicting responses